]
"Multicube: Multi-objective design space exploration of multi-core architectures",
ISVLSI 2010: IEEE Annual Symposium on VLSI, Lixouri, Kefalonia - Greece, pp. 488–493, July, 2010.
"Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors",
2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, Hannover, Germany, February, 2010.
"Multicube Explorer - A Design Space Exploration Framework for Embedded Systems-on-Chip",
Proceedings of the DATE'09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Nice, France, April, 2009.
"MPSoCs Run-Time Monitoring through Networks-on-Chip",
The 2009 Conference on Design, Automation and Test In Europe (DATE'09), Nice, France, April/2009.
"Moving Convolutional Neural Networks to Embedded Systems: The Alexnet and VGG-16 Case",
Proceedings of the 17th ACM/IEEE International Conference on Information Processing in Sensor Networks, Piscataway, NJ, USA, IEEE Press, 2018.
"A Monitoring System for NoCs",
Proceedings of the Third International Workshop on Network on Chip Architectures (NoCArc'2010), Atlanta, Georgia, USA, December, 2010.
"Modelling the Power Cost of Security in Wireless Sensor Networks : the Case of 802.15.4",
Proceedings of IEEE ICT08, Saint Petersburg, Russia, June, 2008.
"Modeling Requirements For Security-enhanced Design of Embedded Systems",
ICETE SECRYPT, Vienna, Austria, ICETE, 08/2014.
"Model-driven approach to design ICT infrastructure for precision farming",
17th IEEE Conference on Emerging Technologies and Factory Automation (ETFA), Kraków, Poland, IEEE Industrial Electronics Society, 09/2012.
"Model-based Design Space Exploration for RTES with SysML and MARTE",
Proceedings of FDL08, Stuttgart, Germany, September, 2008.
"A Model for the Evaluation of User-Perceived Service Properties",
International Symposium on Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW), Boston, Massachusetts, USA, IEEE Computer Society, May, 2013.
"Midori: A Block Cipher for Low Energy",
21st International Conference on the Theory and Application of Cryptology and Information Security ASIACRYPT 2015, vol. 9453, Auckland, New Zealand, Springer Berlin Heidelberg, pp. 411-436, 11/2015.
"Middleware Approaches for Adaptivity of Kahn Process Networks on Networks-on-Chip",
DASIP'11: Proceedings of the Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, pp. 1–8, November 2-4, 2011.
"A Methodology for Testing IPSec-based Systems",
SoftCOM 2004, Split, pp. 22-26, October, 2004.
"A Methodology for Proactive Maintenance of Uninterruptible Power Supplies",
Latin-American Symposium on Dependable Computing (LADC2016) - Workshop on Dependability in Evolving Systems (WDES), Cali, Colombia, 10/2016.
"A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems",
SAC 2003, Melbourne, pp. 672-678, March, 2003.
"Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip",
Euromicro Proceedings of DSD'09 - Conference on Digital System Design, Patras, Greece, August, 2009.
"A Memory Unit for Priority Management in IPSec Accelerators",
proceedings of ICC07. Glasgow, Scotland: IEEE Communications Society, Glasgow, Scotland, June 24, 2007.
"Mapping and Topology Customization Approaches for Application-Specific STNoC Designs",
IEEE Proceedings of ASAP'07 - 18th International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec, Canada, July, 2007.
"Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch",
International Symposium on Electromagnetic Compatibility 2014, 08/2014.