"Design of Fault Tolerant Network Interfaces for NoCs", Proceedings of 14th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'11), Oulu, Finland, September, 2011.
"A Monitoring System for NoCs", Proceedings of the Third International Workshop on Network on Chip Architectures (NoCArc'2010), Atlanta, Georgia, USA, December, 2010.
"Security in NoC", Networks-on-Chips: Theory and Practice: Taylor and Francis Group, LLC - CRC Press, pp. 157-194, 2009.
"Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoCs", Proceedings of the 21st IPDPS 2007 Reconfigurable Architecture Workshop (RAW), 21th IEEE International Parallel and Distributed Processing Symposium, Miami, USA/FL, April, 2008.
"A Security Monitoring Service for NoCs", Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'08), Atlanta, Georgia, USA., 10/2008.
"Fault-Tolerant Network Interfaces for Networks-on-Chip", IEEE Trans. Dependable Secur. Comput., vol. 11, issue 1, pp. 16–29, 01/2014.
"Secure Memory Accesses on Networks-on-Chip", IEEE Transactions on Computers, vol. 57, no. 9, pp. 1216-1229, September, 2008.
"Development cost and size estimation starting from high-level specifications", CODES '01: Proceedings of the ninth international symposium on Hardware/software codesign, Copenhagen, Denmark, ACM Press, New York, USA, pp. 86-91, 2001.
"Hardware Trojans for Inducing or Amplifying Side-Channel Leakage of Cryptographic Software", 2nd International Conference on Trusted Systems (INTRUST), Beijing, China, December, 2010.
"AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies", Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, New York, USA, Springer, pp. 149–184, 2011.
"Solving Multiobjective Optimization Problems in Unknown Dynamic Environments: An Inverse Modeling Approach", IEEE Transactions on Cybernetics, vol. 47, issue 12, pp. 4223 - 4234, 11/2016, 2017.
"Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes", International Conference on VLSI Design & Embedded Systems, Bangalore, India, January 6-10, 2007.
"A Question Answering service for information retrieval in Cooper", COOPER Workshop in conjunction with EC-TEL07 Conference, September 17, 2007.
"(THOR) - The hardware onion router", 24th International Conference on Field Programmable Logic and Applications, (FPL) 2014, Munich, Germany, IEEE, 09/2014.
"Simulation and Analysis of Negative-Bias Temperature Instability Aging on Power Analysis Attacks", IEEE Int. Symposium on Hardware-Oriented Security and Trust, McLean, VA, USA, 05/2015.
"Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags", Springer Journal of Cryptographic Engineering, vol. 1, issue 1, 2011.
"200 MS/s ADC implemented in a FPGA employing TDCs", FPGA International Symposium on Field-Programmable Gate Arrays ACM/SIGDA 2015, Monterey, CA, USA, ACM, pp. 228-235, 02/2015.
"On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography", IEEE Transaction on Computers, In Press.
"Standard lattices in hardware", Proceedings of the 53rd Annual Design Automation Conference DAC 2016, Austin, TX, USA, ACM, pp. 162, 06/2016.
"A Framework for Disturbance Analysis in Smart Grids by Fault Injection", Springer Journal on "Computer Science - Research and Development", 09/2016.