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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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F
Fiorin, L., S. Luković, and G. Palermo, "Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoCs", Proceedings of the 21st IPDPS 2007 Reconfigurable Architecture Workshop (RAW), 21th IEEE International Parallel and Distributed Processing Symposium, Miami, USA/FL, April, 2008.
Fiorin, L., A. Ferrante, K. Padarnitsas, and F. Regazzoni, "Security Enhanced Linux on Embedded Systems: a Hardware-accelerated Implementation", 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, 02/2012.
Fiorin, L., G. Palermo, and C. Silvano, "A Security Monitoring Service for NoCs", Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'08), Atlanta, Georgia, USA., 10/2008.
Fiorin, L., L. Micconi, and M. Sami, "Design of Fault Tolerant Network Interfaces for NoCs", Proceedings of 14th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'11), Oulu, Finland, September, 2011.
Fiorin, L., G. Palermo, and C. Silvano, "A Monitoring System for NoCs", Proceedings of the Third International Workshop on Network on Chip Architectures (NoCArc'2010), Atlanta, Georgia, USA, December, 2010.
Fiorin, L., G. Palermo, C. Silvano, and H. Elmiligi, "Security in NoC", Networks-on-Chips: Theory and Practice: Taylor and Francis Group, LLC - CRC Press, pp. 157-194, 2009.
Fiorin, L., G. Palermo, S. Luković, and C. Silvano, "A Data protection Unit for NoC-based Architecture", CODES+ISSS 2007, in proceedings of the Fifth IEEE/ACM/FIP International Conference of Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), Salzburg, Austria, September 30, 2007.
Fornaciari, W., F. Salice, U. Bondi, and E. Magini, "Development cost and size estimation starting from high-level specifications", CODES '01: Proceedings of the ninth international symposium on Hardware/software codesign, Copenhagen, Denmark, ACM Press, New York, USA, pp. 86-91, 2001.
G
Gallais, J-F., J. Großschädl, N. Hanley, M. Kasper, M. Medwed, F. Regazzoni, J-M. Schmidt, S. Tillich, and M. Wojcik, "Hardware Trojans for Inducing or Amplifying Side-Channel Leakage of Cryptographic Software", 2nd International Conference on Trusted Systems (INTRUST), Beijing, China, December, 2010.
Gamrat, C., J-M. Philippe, C. Jesshope, A. Shafarenko, L. Bisdounis, U. Bondi, A. Ferrante, J. Cabestany, M. Huebner, J. Parsinnen, et al., "AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies", Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, New York, USA, Springer, pp. 149–184, 2011.
Gee, S. Bong, K. Chen Tan, and C. Alippi, "Solving Multiobjective Optimization Problems in Unknown Dynamic Environments: An Inverse Modeling Approach", IEEE Transactions on Cybernetics, vol. 47, issue 12, pp. 4223 - 4234, 11/2016, 2017.
Giaconia, M., M. Macchetti, F. Regazzoni, and K. Schramm, "Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes", International Conference on VLSI Design & Embedded Systems, Bangalore, India, January 6-10, 2007.
Giesbers, B., A V. Taddeo, W. van der Vegt, J. van Bruggen, and R. Koper, "A Question Answering service for information retrieval in Cooper", COOPER Workshop in conjunction with EC-TEL07 Conference, September 17, 2007.
Güneys, T., F. Regazzoni, P. Sasdrich, and M. Wojcik, "(THOR) - The hardware onion router", 24th International Conference on Field Programmable Logic and Applications, (FPL) 2014, Munich, Germany, IEEE, 09/2014.
Guo, X., N. Karimi, F. Regazzoni, C. Jin, and R. Karri, "Simulation and Analysis of Negative-Bias Temperature Instability Aging on Power Analysis Attacks", IEEE Int. Symposium on Hardware-Oriented Security and Trust, McLean, VA, USA, 05/2015.
H
Hocquet, C., D. Kamel, F. Regazzoni, J-D. Legat, D. Flandre, D. Bol, and F-X. Standaert, "Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags", Springer Journal of Cryptographic Engineering, vol. 1, issue 1, 2011.
Homulle, H., F. Regazzoni, and E. Charbon, "200 MS/s ADC implemented in a FPGA employing TDCs", FPGA International Symposium on Field-Programmable Gate Arrays ACM/SIGDA 2015, Monterey, CA, USA, ACM, pp. 228-235, 02/2015.
Howe, J., C. Moore, M. O'Neill, F. Regazzoni, T. Güneysu, and K.. Beeden, "Standard lattices in hardware", Proceedings of the 53rd Annual Design Automation Conference DAC 2016, Austin, TX, USA, ACM, pp. 162, 06/2016.
Howe, J., A. Khalid, C. Rafferty, F. Regazzoni, and M. O'Neill, "On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography", IEEE Transaction on Computers, In Press.

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