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"Mapping and Topology Customization Approaches for Application-Specific STNoC Designs", IEEE Proceedings of ASAP'07 - 18th International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec, Canada, July, 2007.
"Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations", DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07), Lübeck, Germany, August 29-31, 2007.
"A Topology Design Customization Approach for (STNoC)", Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007)., Catania, Italy, September 24-26, 2007.
"A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems", SAC 2003, Melbourne, pp. 672-678, March, 2003.
"Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering", 39th Design Automation Conference, New Orleans, pp. 886-891, June 10-14, 2002.
"An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW cores", DATE 2002, Paris, pp. 1128, March 4-8, 2002.