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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Vukmirović, S., S. Luković, A. Erdeljan, and F. Kulić, "An enhanced workflow management for Utility Management System", Proceedings of the International Congress on Ultra Modern Telecommunications and Control Systems (ICUMT 2010), Moscow, Russia, October 18-20, 2010.
Luković, S., and N. Christianos, "Enhancing Network-on-Chip Components to Support Security of Processing Elements", Proceedings of the 5th Workshop on Embedded Systems Security (WESS'2010) A Workshop of the Embedded Systems Week (ESWEEK '10), Scottsdale, AZ, USA, October 24, 2010.
Bu, L., C. Alippi, and D. Zhao, "Ensemble LSDD-based Change Detection Tests", IEEE-INNS International Joint Conference on Neural Networks (IJCNN16), Vancouver, Canada, 07/2016.
Regazzoni, F., T. Eisenbarth, A. Poschmann, J. Groschdl, F. Gurkaynak, M. Macchetti, Z. Toprak, L. Pozzi, C. Paar, Y. Leblebici, et al., "Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology", Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
Mariani, G., G. Palermo, V. Zaccaria, and C. Silvano, "Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework", Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, February, 2012.
Bellon, S., C. Favi, M. Malek, M. Macchetti, and F. Regazzoni, "Evaluating the Impact of Environmental Factors on Physically Unclonable Functions", International Symposium on Field-Programmable Gate Arrays FPGA 2016, Monterey, CA, USA, ACM New York, NY, USA, pp. 279, 02/2016.
Dittrich, A., S. Wanja, and M. Malek, "ExCovery – A Framework for Distributed System Experiments and a Case Study of Service Discovery", 28th International Parallel & Distributed Processing Symposium, Workshops and Phd Forum (IPDPSW), Phoenix, AZ, USA, IEEE Computer Society, 05/2014.
Mura, M., A. Panda, and M. Prevostini, "Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities", Proceedings of MARTE Workshop (DATE08), Munich, Germany, March, 2008.
Banik, S., A. Bogdanov, and F. Regazzoni, "Exploring Energy Efficiency of Lightweight Block Ciphers", (IACR) Cryptology ePrint Archive, vol. 2015, 09/2015.
Banik, S., A. Bogdanov, and F. Regazzoni, "Exploring Energy Efficiency of Lightweight Block Ciphers", Selected Areas in Cryptography: 22nd International Conference (SAC)2015, vol. 9566, Sackville, NB, Canada, Springer, pp. 178-194, 08/2015.
Banik, S., A. Bogdanov, and F. Regazzoni, "Exploring the energy consumption of lightweight blockciphers in FPGA", International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, 2015, Rivera Maya, Mexico City, IEEE, pp. 1-6, 02/2016, 2015.
Barenghi, A., C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni, and I. Koren, "Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices through an Example of a 65nm AES Implementation", 7th Workshop on RFID Security and Privacy (RFIDSec), Amherst, Massachussets, USA, June, 2011.
Valencia, F., T. Oder, T. Güneysu, and F. Regazzoni, "Exploring the Vulnerability of R-LWE Encryption to Fault Attacks", Workshop on Cryptography and Security in Computing Systems of the HiPEAC2018 Conference, CS2 '18, New York, NY, USA, ACM, 2018.
Ferrante, A., M. Malek, F. Martinelli, F. Mercaldo, and J. Milosevic, "Extinguishing Ransomware - A Hybrid Approach to Android Ransomware Detection", Foundations and Practice of Security, vol. 10723, Cham, Springer International Publishing, pp. 242-258, 02/2018.
Bol, D., C. Hocquet, and F. Regazzoni, "A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints", IEEE Transactions on Circuits and Systems II, vol. 59, issue 12, pp. 947-951, 2013.
Bol, D., C. Hocquet, and F. Regazzoni, "A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints", IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 59-II, issue 12, pp. 947-951, 02/2012.
Piscitelli, R., S. Bhasin, and F. Regazzoni, "Fault attacks, injection techniques and tools for simulation", 10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015, Naples, Italy, IEEE, pp. 1-6, 04/2015.
Piscitelli, R., S. Bhasin, and F. Regazzoni, "Fault Attacks, Injection Techniques and Tools for Simulation", Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, First edition; 2016: Springer, pp. 149-167, 2017.
Fiorin, L., and M. Sami, "Fault-Tolerant Network Interfaces for Networks-on-Chip", IEEE Trans. Dependable Secur. Comput., vol. 11, issue 1, pp. 16–29, 01/2014.
Bayrak, A. Galip, F. Regazzoni, P. Brisk, F-X. Standaert, and P. Ienne, "A First Step Towards Automatic Application of Power Analysis Countermeasures", 48th Design Automation Conference (DAC), San Diego, Califorina, June, 2011.