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Filters: Author is Francesco Regazzoni [Clear All Filters]
"Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes", International Conference on VLSI Design & Embedded Systems, Bangalore, India, January 6-10, 2007.
"Adaptable AES implementation with power-gating support", International Conference on Computing Frontiers CF'16, Como, Italy, ACM Ney York, NY, USA, pp. 331-334, 05/2016.
"Accelerating differential power analysis on heterogeneous systems", The 9th Workshop on Embedded Systems Security (WESS) 2014, New Delhi, India, ACM, 10/2014.
"A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm", SECRYPT, Porto, Portugal, July 26, 2008.
"200 MS/s ADC implemented in a FPGA employing TDCs", FPGA International Symposium on Field-Programmable Gate Arrays ACM/SIGDA 2015, Monterey, CA, USA, ACM, pp. 228-235, 02/2015.