Export 105 results:
Author Title Type [ Year] Filters: Author is Francesco Regazzoni [Clear All Filters]
"Speeding Up AES By Extending a 32 bit Processor Instruction Set",
ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), Washington, DC, USA, IEEE Computer Society, pp. 275-282, 2006.
"Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures",
FDL'05 - Forum on Specification and Design Languages, Lausanne, Switzerland, September 27-30, 2005.
"Hardware/Software Partitioning and Interface Synthesis in Networks On Chip",
IP Based SoC Design 2005, Grenoble, France, December 7-8, 2005.
"Speeding Security on the Intel StrongARM",
Embedded Intel Solutions, pp. 31-33, 2005.
"Interface Synthesis in Multiprocessing Systems-on-Chips",
IP Based SoC Design 2004, Grenoble, December, 2004.