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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Conference Paper
Peña, J., A. Upegui, and E. Sanchez, "Particle Swarm Optimization with Discrete Recombination: An Online Optimizer for Evolvable Hardware", 1st NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2006), Istanbul, Turkey, June 16-18, 2006.
Regazzoni, F., T. Eisenbarth, J. Großschädl, L. Breveglieri, P. Ienne, I. Koren, and C. Paar, "Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits", proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
Mura, M., M. Paolieri, L. Negri, F. Fabbri, and M. Sami, "Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach", Proceedings of CCNC 2007, Las Vegas, USA, January 11-13, 2007.
Ferrante, A., R. Pompei, A. Stulova, and A V. Taddeo, "A Protocol For Pervasive Distributed Computing Reliability", SecPri_WiMob 2008, Avignon, France, IEEE, 10/2008.
Regazzoni, F., A. Fowler, and I. Polian, "Quantum Era Challenges for Classical Computers", Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY, USA, ACM, 2018.
Ferrante, A., S. Chandra, and V. Piuri, "A Query Unit for the IPSec Databases", SECRYPT 2007, Barcelona, Spain, 07/2007.
Tumeo, A., F. Regazzoni, G. Palermo, F. Ferrandi, and D. Sciuto, "A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation", Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.
Paolieri, M., I. Bonesana, and M D. Santambrogio, "ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching", Proceedings of 15th Annual IFIP International Conference on Very Large Scale Integration {(IFIP-VLSI 07)},(best paper award), Atlanta, Georgia, USA, October 15-17, 2007.
Upasani, G., A. Calimera, A. Macii, E. Macii, and M. Poncino, "Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering", Proceedings of the 19th international workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009), Delft, The Netherlands, September 9-11, 2009.
Mariani, G., V-M. Sima, G. Palermo, V. Zaccaria, G. Marchiori, C. Silvano, and K. Bertels, "Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction", 23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, IEEE, 09/2013.
Mura, M., and M. Paolieri, "SC2: State Charts to System C: Automatic Executable Models Generation", proceedings FDL07, Barcelona, Spain, September, 2007.
Taddeo, A V., A. Ferrante, and V. Piuri, "Scheduling Small Packets in IPSec-based Systems", CCNC, Las Vegas, NV, USA, January 8, 2006.
Baddour, R., A. Paspaliaris, and D. Solis Herrera, "SCV2: A model-based validation and verification approach to system-of-systems engineering", System of Systems Engineering Conference (SoSE), 2015 10th: IEEE, 05/2015.
Fiorin, L., A. Ferrante, K. Padarnitsas, and F. Regazzoni, "Security Enhanced Linux on Embedded Systems: a Hardware-accelerated Implementation", 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, 02/2012.
Fiorin, L., G. Palermo, and C. Silvano, "A Security Monitoring Service for NoCs", Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'08), Atlanta, Georgia, USA., 10/2008.
Regazzoni, F., C. Alippi, and I. Polian, "Security: The Dark Side of Approximate Computing?", Proceedings of the International Conference on Computer-Aided Design, New York, NY, USA, ACM, 11/2018.
Murillo, L G., M. Mura, and M. Prevostini, "Semi-Automated HW/SW Co-design for Embedded Systems: from MARTE Models to SystemC Simulators", FDL'09 Proceedings, Sophia-Antipolis, France, September 22-24, 2009.
Regazzoni, F., S. Badel, T. Eisenbarth, J. Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, L. Pozzi, C. Paar, Y. Leblebici, et al., "Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies", International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
Regazzoni, F., S. Badel, T. Eisenbarth, J. Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, L. Pozzi, C. Paar, Y. Leblebici, et al., "Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies", International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
Regazzoni, F., S. Badel, T. Eisenbarth, J. Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, L. Pozzi, C. Paar, Y. Leblebici, et al., "Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies", International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.

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