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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Filters: Author is Francesco Regazzoni  [Clear All Filters]
Conference Paper
Banik, S., A. Bogdanov, and F. Regazzoni, "Efficient Configurations for Block Ciphers with Unified ENC/DEC Paths", Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2017, 2018.
Bayrak, A. Galip, N. Velickovic, F. Regazzoni, D. Novo Bruna, P. Brisk, and P. Ienne, "An eda-friendly protection scheme against side-channel attacks", Design, Automation and Test in Europe (DATE), Grenoble, France, March, 2013.
Valencia, F., A. Khalid, E. O'Sullivan, and F. Regazzoni, "The design space of the number theoretic transform: A survey", 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, {SAMOS} 2017, Pythagorion, Greece, July 17-20, 2017 (Invited), 2017.
Faruque, M. Abdullah A., F. Regazzoni, and M. Pajic, "Design methodologies for securing cyber-physical systems", 2015 International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS, Amsterdam, Netherlands, IEEE, pp. 30-36, 10/2015.
Masin, M., F. Palumbo, H. Myrhaug, J. A. de Oliv Filho, M. Pastena, M. Pelcat, L. Raffo, F. Regazzoni, A. A. Sanchez, A. Toffetti, et al., "Cross-layer Design of Reconfigurable Cyber-Physical Systems", Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
Powolny, F., S. Burri, C. Bruschini, X. Michalet, F. Regazzoni, and E. Charbon, "Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADS) for Fluorescence Lifetime Imaging Application with Picosecond Resolution", International Image Sensor Workshop (IISW), Snowbird Resort, Utah, USA, June, 2013.
Khalid, A., J. Howe, C. Rafferty, F. Regazzoni, and M. O'Neil, "Compact, Scalable, and Efficient Gaussian Samplers for Lattice-Based Cryptography", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018, 2018.
Balasch, J., B. Ege, T. Eisenbarth, B. Grard, Z. Gong, T. Gneysu, S. Heyse, S. Kerckhof, F. Koeune, T. Plos, et al., "Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices", 11th Smart Card Research and Advanced Application Conference (CARDIS), Graz, Austria, November, 2012.
Eisenbarth, T., Z. Gong, T. Gneysu, S. Heyse, S. Indesteege, S. Kerckhof, F. Koeune, T. Nad, T. Plos, F. Regazzoni, et al., "Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices", Progress in Cryptology - Africacrypt, Ifrance, Morocco, July, 2012.
Regazzoni, F., R. Graves, G. Di Natale, L. Batina, S. Bhasin, B. Ege, A. P. Fournaris, N. Mentens, S. Picek, V. Rozic, et al., "Challenges in designing trustworthy cryptographic co-processors", IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal, IEEE, pp. 2009-2012, 09/2015.
Bailey, D. V., B. Baldwin, L. Batina, D. J. Bernstein, P. Birkner, J. W. Bos, G. van Damme, G. de Meulenaer, J. Fan, F. Gurkaynak, et al., "The Certicom Challenges ECC2-X", Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS), Lausanne, Switzerland, September, 2009.
Regazzoni, F., T. Eisenbarth, L. Breveglieri, P. Ienne, and I. Koren, "Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?", Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), October 1-3, 2008.
Regazzoni, F., A C. Nacul, and M. Lajolo, "Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures", FDL'05 - Forum on Specification and Design Languages, Lausanne, Switzerland, September 27-30, 2005.
Banik, S., A. Bogdanov, and F. Regazzoni, "Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core", Proceedings of 17th International Conference on Cryptology in India (INDOCRYPT) 2016, 2016.
Giaconia, M., M. Macchetti, F. Regazzoni, and K. Schramm, "Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes", International Conference on VLSI Design & Embedded Systems, Bangalore, India, January 6-10, 2007.
Banik, S., A. Bogdanov, T. Fanni, C. Sau, L. Raffo, F. Palumbo, and F. Regazzoni, "Adaptable AES implementation with power-gating support", International Conference on Computing Frontiers CF'16, Como, Italy, ACM Ney York, NY, USA, pp. 331-334, 05/2016.
Amaral, J., F. Regazzoni, P. Tomas, and R. Chaves, "Accelerating differential power analysis on heterogeneous systems", The 9th Workshop on Embedded Systems Security (WESS) 2014, New Delhi, India, ACM, 10/2014.
Bertoni, G M., L. Breveglieri, R. Farina, and F. Regazzoni, "A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm", SECRYPT, Porto, Portugal, July 26, 2008.
Homulle, H., F. Regazzoni, and E. Charbon, "200 MS/s ADC implemented in a FPGA employing TDCs", FPGA International Symposium on Field-Programmable Gate Arrays ACM/SIGDA 2015, Monterey, CA, USA, ACM, pp. 228-235, 02/2015.
Book Chapter
Durvaux, F., S. Kerckhof, F. Regazzoni, and F-X. Standaert, "Security IPs and IP Security with FPGAs", Secure Smart Embedded Devices Platform and Applications, 2014.