Export 105 results:
Author [ Title
] Type Year Filters: Author is Francesco Regazzoni [Clear All Filters]
"The design space of the number theoretic transform: A survey",
2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, {SAMOS} 2017, Pythagorion, Greece, July 17-20, 2017 (Invited), 2017.
"Design methodologies for securing cyber-physical systems",
2015 International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS, Amsterdam, Netherlands, IEEE, pp. 30-36, 10/2015.
"A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions",
Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.
"Customized Instructions for Protection Against Memory Integrity Attacks",
IEEE Embedded Systems Letters, In Press.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems",
Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
"Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADS) for Fluorescence Lifetime Imaging Application with Picosecond Resolution",
International Image Sensor Workshop (IISW), Snowbird Resort, Utah, USA, June, 2013.
"Compact, Scalable, and Efficient Gaussian Samplers for Lattice-Based Cryptography",
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018, 2018.
"Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices",
11th Smart Card Research and Advanced Application Conference (CARDIS), Graz, Austria, November, 2012.
"Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices",
Progress in Cryptology - Africacrypt, Ifrance, Morocco, July, 2012.
"Compact Circuits for Combined AES",
Journal of Cryptographic Engineering, In Press.
"A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks",
IEEE Transactions on Emerging Topics in Computing, vol. PP, issue 99, 04/2014.
"Challenges in designing trustworthy cryptographic co-processors",
IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal, IEEE, pp. 2009-2012, 09/2015.
"The Certicom Challenges ECC2-X",
Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS), Lausanne, Switzerland, September, 2009.
"Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?",
Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), October 1-3, 2008.
"Breaking ECC2K-130",
IACR Cryptology ePrint Archive, vol. 2009, pp. 541, 11/2009.
"Black-Hat High-Level Synthesis: Myth or Reality?",
IEEE Transactions on Very Large Scale Integration Systems, In Press.
"Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures",
FDL'05 - Forum on Specification and Design Languages, Lausanne, Switzerland, September 27-30, 2005.
"Automatic Application of Power Analysis Countermeasures",
IEEE Transactions on Computers , vol. 64, issue 2, pp. 329-341, 02/2015.
"Automatic Application of Power Analysis Countermeasures",
IEEE Transactions on Computers, vol. PP, issue 99, 12/2013.
"Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core",
Proceedings of 17th International Conference on Cryptology in India (INDOCRYPT) 2016, 2016.