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"Low Cost FPGA Implementations of the SHA-3 Finalists", 10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
"Low Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs", 5th Workshop on Embedded Systems Security (WESS), Scottsdale, Arizona, USA, October, 2010.
"Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch", International Symposium on Electromagnetic Compatibility 2014, 08/2014.
"Malware Threats and Solutions for Trustworthy Mobile Systems Design", Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, First edition; 2016: Springer, pp. 149-167, 2017.
"Midori: A Block Cipher for Low Energy", 21st International Conference on the Theory and Application of Cryptology and Information Security ASIACRYPT 2015, vol. 9453, Auckland, New Zealand, Springer Berlin Heidelberg, pp. 411-436, 11/2015.
"Midori: (A) Block Cipher for Low Energy (Extended Version)", (IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
"Physical Attacks and Beyond", Proceedings of the Selected Areas in Cryptography: 23nd International Conference (SAC) 2016, 2016.
"Physical attacks, introduction and application to embedded processors", 10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015, Napoli, Italy, IEEE, pp. 1, 06/2015.
"Power and Performance Optimized Hardware Classifiers for Eefficient On-device Malware Detection", Cryptography and Security in Computing Systems, Valencia, Spain, ACM, 01/2019.
"Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits", proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
"Power-Gated MOS Current Mode Logic (PG-MCML): A Power-Aware DPA-Resistant Standard Cell Library", 48th Design Automation Conference (DAC), San Diego, Califorina, June, 2011.
"On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography", IEEE Transaction on Computers, In Press.
"Quantum Era Challenges for Classical Computers", Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY, USA, ACM, 2018.
"Rapid Creation of Application Models from Bandwidth Aware Core Graphs", Proceedings of: IP Based SoC Design 2007, Grenoble, France, December 5-6, 2007.
Reconfigurable Logic Circuit, , no. GB1719355.8, 11/2017, Submitted.
"A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation", Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.
"Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow", Proceedings of FCCM, 05/2018.
"Round gating for low energy block ciphers", 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST, McLean, VA, USA, IEEE Computer Society, pp. 55-60, 05/2016.
"SCA-Resistance for AES: How Cheap Can We Go?", Progress in Cryptology – AFRICACRYPT 2018, Cham, Springer International Publishing, 2018.
"Secure architectures of future emerging cryptography", International Conference on Computing Frontiers CF'16, Como, italy, ACM New York, pp. 315-322, 05/2016.