Export 140 results:
Author Title [ Type
] Year Filters: First Letter Of Last Name is P [Clear All Filters]
"Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies",
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
"Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies",
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
"Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies",
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
"Semi-Automated HW/SW Co-design for Embedded Systems: from MARTE Models to SystemC Simulators",
FDL'09 Proceedings, Sophia-Antipolis, France, September 22-24, 2009.
"Security: The Dark Side of Approximate Computing?",
Proceedings of the International Conference on Computer-Aided Design, New York, NY, USA, ACM, 11/2018.
"A Security Monitoring Service for NoCs",
Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'08), Atlanta, Georgia, USA., 10/2008.
"Security Enhanced Linux on Embedded Systems: a Hardware-accelerated Implementation",
17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, 02/2012.
"SCV2: A model-based validation and verification approach to system-of-systems engineering",
System of Systems Engineering Conference (SoSE), 2015 10th: IEEE, 05/2015.
"Scheduling Small Packets in IPSec-based Systems",
CCNC, Las Vegas, NV, USA, January 8, 2006.
"SC2: State Charts to System C: Automatic Executable Models Generation",
proceedings FDL07, Barcelona, Spain, September, 2007.
"Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction",
23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, IEEE, 09/2013.
"Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering",
Proceedings of the 19th international workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009), Delft, The Netherlands, September 9-11, 2009.
"ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching",
Proceedings of 15th Annual IFIP International Conference on Very Large Scale Integration {(IFIP-VLSI 07)},(best paper award), Atlanta, Georgia, USA, October 15-17, 2007.
"A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation",
Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.
"A Query Unit for the IPSec Databases",
SECRYPT 2007, Barcelona, Spain, 07/2007.
"Quantum Era Challenges for Classical Computers",
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY, USA, ACM, 2018.
"A Protocol For Pervasive Distributed Computing Reliability",
SecPri_WiMob 2008, Avignon, France, IEEE, 10/2008.
"Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach",
Proceedings of CCNC 2007, Las Vegas, USA, January 11-13, 2007.
"Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits",
proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
"Particle Swarm Optimization with Discrete Recombination: An Online Optimizer for Evolvable Hardware",
1st NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2006), Istanbul, Turkey, June 16-18, 2006.