Export 140 results:
Author Title [ Type
] Year Filters: First Letter Of Last Name is P [Clear All Filters]
"DarkMem: Fine-Grained Power Management of Local Memories for Accelerators in Embedded Systems",
Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2018.
"A Data protection Unit for NoC-based Architecture",
CODES+ISSS 2007, in proceedings of the Fifth IEEE/ACM/FIP International Conference of Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), Salzburg, Austria, September 30, 2007.
"Design and Synthesis of Reusable Platforms with Programmable Interconnects",
UML-SoC 2005, Anaheim, California, pp. 43-48, June 12, 2005.
"Design methodologies for securing cyber-physical systems",
2015 International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS, Amsterdam, Netherlands, IEEE, pp. 30-36, 10/2015.
"A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip",
Proceedings IEEE SASP'09 - Symposium on Application Specific Processors, San Francisco, CA, USA, July, 2009.
"Detecting changes at the sensor level in cyber-physical systems: Methodology and technological implementation",
2017 International Joint Conference on Neural Networks (IJCNN), May, 2017.
"DRuiD: Designing Reconfigurable Architectures with Decision-making Support",
19th Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, 01/2014.
"Efficient C implementation of the ECC and AES cryptographic systems",
Technology Leadership Day - organized by the MicroSwiss Network, Fribourg, October 10, 2001.
"An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks",
Proc. IFIP International Conference on Very Large Scale Integration VLSI - SoC 2008, Rhodes Island, Greece, October 13-15, 2008.
"An Enhanced Service Provider Communication Interface with Client Priorization",
proceedings of IEEE/WFMC International Conference on e-Business, July 26-29, 2008.
"Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework",
Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, February, 2012.
"Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities",
Proceedings of MARTE Workshop (DATE08), Munich, Germany, March, 2008.
"Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities",
Proceedings of MARTE Workshop (DATE08), Munich, Germany, March, 2008.
"Fault attacks, injection techniques and tools for simulation",
10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015, Naples, Italy, IEEE, pp. 1-6, 04/2015.
"Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks",
10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
"Functional model of Virtual Power Plant (VPP)",
Proceedings of the 2010 CIGRE (International Council on Large Electric Systems) Session, Paris, France, July, 2010.
"Hardware-assisted Security Enhanced Linux in Embedded Systems: a Proposal",
Proceedings of the 5th Workshop on Embedded Systems Security (WESS'2010), Scottsdale, Arizona, USA, October 24, 2010.
"High-level Architecture of an IPSec-dedicated System on Chip",
proceedings of NGI 2007, Trondheim, Norway, IEEE Press, May, 2007.
"High-Level Synthesis of Benevolent Trojans",
Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE), 2019.
"Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoCs",
Proceedings of the 21st IPDPS 2007 Reconfigurable Architecture Workshop (RAW), 21th IEEE International Parallel and Distributed Processing Symposium, Miami, USA/FL, April, 2008.