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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Mariani, G., G. Palermo, V. Zaccaria, and C. Silvano, "An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks", Proc. IFIP International Conference on Very Large Scale Integration VLSI - SoC 2008, Rhodes Island, Greece, October 13-15, 2008.
Mariani, G., G. Palermo, C. Silvano, and V. Zaccaria, "Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip", Euromicro Proceedings of DSD'09 - Conference on Digital System Design, Patras, Greece, August, 2009.
Mariani, G., G. Palermo, V. Zaccaria, and C. Silvano, "ARTE: an Application-specific Run-Time Management Framework for Multi-cores based on Queuing Models", Parallel Computing, 2013.
Mariani, G., V-M. Sima, G. Palermo, V. Zaccaria, G. Marchiori, C. Silvano, and K. Bertels, "Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction", 23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, IEEE, 09/2013.
Mariani, G., G. Palermo, V. Zaccaria, A. Brankovic, J. Jovic, and C. Silvano, "A Correlation-based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip", Proceedings of DAC 2010: Design Automation Conference, Anheim, CA, USA, pp. 120–125, June, 2010.
Mariani, G., G. Palermo, V. Zaccaria, and C. Silvano, "Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework", Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, February, 2012.
Mariani, G., G. Palermo, C. Silvano, and V. Zaccaria, "OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Space", IEEE Transactions on Computer-Aided Design, vol. 21, issue 5, no. -: IEEE, pp. 740-753, 05/2012.
Mariani, G., G. Palermo, C. Silvano, and V. Zaccaria, "ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems", Proceedings IEEE SASP'11 - Symposium on Application Specific Processors, San Diego, CA, USA, June, 2011.
Mariani, G., R. Meeuws, G. Palermo, V-M. Sima, C. Silvano, and K. Bertels, "DRuiD: Designing Reconfigurable Architectures with Decision-making Support", 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, 01/2014.
Mariani, G., G. Palermo, C. Silvano, and V. Zaccaria, "A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip", Proceedings IEEE SASP'09 - Symposium on Application Specific Processors, San Francisco, CA, USA, July, 2009.
Mariani, G., V-M. Sima, G. Palermo, V. Zaccaria, C. Silvano, and K. Bertels, "Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures", Proc. Design, Automation Test in Europe Conf. Exhibition (DATE), March, 2012.
Malek, M., "Securability: the Key Challenge for Autonomic and Trusted Computing", IEEE International Conference on Ubiquitous Intelligence Computing / International Conference on Autonomic Trusted Computing (UIC/ATC), 9, 03/2012.
Malek, M., "Predictive Analytics: A Shortcut to Dependable Computing", Software Engineering for Resilient Systems, Cham, Springer International Publishing, 2017.
Mady, A E-D., A. Tonini, and D. Finardi, "Design Space Exploration of PISA Architecture For ONU Auto-discovery Process", proceedings of 6th International Conference of Electrical Engineering (ICEENG), Cairo, Egypt, May 27-29, 2009.
Macchetti, M., and G M. Bertoni, "Hardware Implementation of the Rijndael Sbox: a Case Study", ST Journal of System Research, pp. 84-91, July, 2003.
Macchetti, M., and P. Rivard, "Small-scale Variants of the Secure Hash Standard", ECRYPT workshop on RFID and lightweight cryptography, Graz, Austria, July 14-15, 2005.
Macchetti, M., and L. Dadda, "Quasi-Pipelined Hash Circuits", IEEE ARITH 17, Cape Cod, pp. 222-229, June, 2005.
Macchetti, M., P. Fragneto, and G M. Bertoni, Method of implementing one-to-one binary function and relative hardware device, especially for a Rijndael S-box, , no. US 10/816,791 -- EP 20030425211, 10/2004.
Macchetti, M., and W. Chen, "ASIC Hardware Implementation of the IDEA NXT Encryption Algorithm", IEEE International Symposium on Circuits and Systems, Kos, Greece, May 21-24, 2006.
Macchetti, M., S. Marchesin, U. Bondi, L. Breveglieri, G M. Bertoni, and P. Fragneto, Method and circuit for data encryption/decryption, , no. US 09/974,705, April, 2003.

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