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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Author Title [ Type(Desc)] Year
Conference Paper
Negri, L., and U. Bondi, "The ALaRI Intranet: a Remote Collaboration Platform for a Worldwide Learning and Research Network", World Conference on Educational Multimedia, Hypermedia and Telecommunications 04 (ED-MEDIA 04), Lugano, Switzerland, AACE Press, pp. 5042-5047, 2004.
Ferrante, A., M. Chelodi, F. Bruschi, and V. Mozzetti, "An Algorithm for Extended Dynamic Range Video in Embedded Systems", SENSORNETS 2013 - 2nd International Conference on Sensor Networks, Barcelona, Spain, INSTICC, 02/2013.
Alippi, C., A. Galbusera, and M. Stellini, "An Application Level Synthesis Methodology for Embedded Systems", ISCAS 2002, Scottsdale, pp. 473-476, May 26-29, 2002.
Ferrante, A., G. Piscopo, and S. Scaldaferri, "Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach", RTAS '05: Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium, Washington, DC, USA, IEEE Computer Society, pp. 128–137, 03/2005.
Palermo, G., G. Mariani, C. Silvano, R. Locatelli, and M. Coppola, "Application-Specific Topology Design Customization for STNoC", DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07), Lübeck, Germany, August 29-31, 2007.
Luković, S., A. Gasparin, J. Witzig, and I. Herbst, "Arbon Demonstrator Eye-on-the-Grid, from Concept to Results", SCCER-FURIES Annual Conference, 12/2018.
Giaconia, M., M. Macchetti, F. Regazzoni, and K. Schramm, "Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes", International Conference on VLSI Design & Embedded Systems, Bangalore, India, January 6-10, 2007.
Mariani, G., G. Palermo, C. Silvano, and V. Zaccaria, "ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems", Proceedings IEEE SASP'11 - Symposium on Application Specific Processors, San Diego, CA, USA, June, 2011.
Dadda, L., M. Macchetti, and J. Owen, "An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)", GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI, Boston, MA, USA, ACM Press, New York, USA, pp. 421–425, 2004.
Macchetti, M., and W. Chen, "ASIC Hardware Implementation of the IDEA NXT Encryption Algorithm", IEEE International Symposium on Circuits and Systems, Kos, Greece, May 21-24, 2006.
Banik, S., A. Bogdanov, and F. Regazzoni, "Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core", Proceedings of 17th International Conference on Cryptology in India (INDOCRYPT) 2016, 2016.
Luković, S., and L. Fiorin, "An Automated Design Flow for NoC-based MPSoCs on FPGA", RSP 2008, The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, Monterey, USA/CA, June 2-5, 2008.
Regazzoni, F., A C. Nacul, and M. Lajolo, "Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures", FDL'05 - Forum on Specification and Design Languages, Lausanne, Switzerland, September 27-30, 2005.
Krdu, A., Y. Lebrun, U. Ahmad, S. Pollin, and M. Li, "Beamforming for interference mitigation and its implementation on an SDR baseband processor", SiPS'11: Proceedings of the IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, pp. 1–6, October 4-7, 2011.
Pilato, C., "Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis", Advances in Parallel Computing, 2018.
Sivakumar, G., and M. Prevostini, "Bridging the Gap between SysML and Design Space Exploration", FDL'06 Proceedings, Darmstadt, Germany, pp. 389-394, September 19-22, 2006.
Prevostini, M., A V. Taddeo, K. Balać, M. Jermini, and C. Linder, "Calibration and in-Field Validation Tests of a Web-based Adaptive Management System for Monitoring - Scaphoideus titanus", Future Integrated Pest Management in Europe, 2013.
Regazzoni, F., T. Eisenbarth, L. Breveglieri, P. Ienne, and I. Koren, "Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?", Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), October 1-3, 2008.
Milosevic, J., A. Ferrante, and M. Malek, "Can we Achieve both Privacy Protection and Efficient Malware Detection on Smartphones?", 1st Interdisciplinary Cyber Research Workshop 2015, Tallin, Estona, Tallinn University of Technology, 07/2015.
Bailey, D. V., B. Baldwin, L. Batina, D. J. Bernstein, P. Birkner, J. W. Bos, G. van Damme, G. de Meulenaer, J. Fan, F. Gurkaynak, et al., "The Certicom Challenges ECC2-X", Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS), Lausanne, Switzerland, September, 2009.