"Time series kernel similarities for predicting Paroxysmal Atrial Fibrillation from ECGs",
IJCNN 2018 : International Joint Conference on Neural Networks, Rio, Brazil, IEEE, 07/2018.
"High-Level Synthesis of Benevolent Trojans",
Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE), 2019.
"Power and Performance Optimized Hardware Classifiers for Eefficient On-device Malware Detection",
Cryptography and Security in Computing Systems, Valencia, Spain, ACM, 01/2019.
"Time, Accuracy and Power Consumption Tradeoff in Mobile Malware Detection Systems",
Computers & Security, vol. 82, pp. 314-328, 05/2019.
"Black-Hat High-Level Synthesis: Myth or Reality?",
IEEE Transactions on Very Large Scale Integration Systems, In Press.
"Compact Circuits for Combined AES",
Journal of Cryptographic Engineering, In Press.
"Customized Instructions for Protection Against Memory Integrity Attacks",
IEEE Embedded Systems Letters, In Press.
"Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis",
IEEE Design & Test, 2018, In Press.
"On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography",
IEEE Transaction on Computers, In Press.
"TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In Press.
"Towards Low Energy Stream Ciphers",
IACR Transactions on Symmetric Cryptology, In Press.
Reconfigurable Logic Circuit,
, no. GB1719355.8, 11/2017, Submitted.