]
"Compact Circuits for Combined AES",
Journal of Cryptographic Engineering, In Press.
"Concept Drift and Anomaly Detection in Graph Streams",
IEEE Transactions on Neural Networks and Learning Systems, vol. 29, issue 11, pp. 5592-5605, 11/2018.
"A Configurable Monitoring Infrastructure for NoC-Based Architectures",
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, issue 99, 2013.
"Coordinated management of hardware and software self-adaptivity",
Journal of Systems Architecture, vol. 55, issue 3, no. {3}, pp. 170 - 179, 03/2009.
"Credit Card Fraud Detection: A Realistic Modeling and a Novel Learning Strategy",
IEEE Transactions on Neural Networks and Learning Systems, pp. 1-14, 2018.
"Customized Instructions for Protection Against Memory Integrity Attacks",
IEEE Embedded Systems Letters, In Press.
"Design-space Exploration and Runtime Resource Management for Multicores",
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors, vol. 13, issue 2, pp. 20:1–20:27, 09/2013.
"Determination of the Edge of Criticality in Echo State Networks Through Fisher Information Maximization",
IEEE Transactions on Neural Networks and Learning Systems, vol. 29, pp. 706-717, March, 2018.
"Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis",
IEEE Design & Test, 2018, In Press.
"Enabling Self-adaptivity in Component-based Streaming Applications",
ACM SIGBED Review - Special Issue on the 2nd International Workshop on Adaptive and Reconfigurable Embedded Systems, vol. 6, no. {3}: ACM SIGBED, pp. 14:1-14:4, 10/2009.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology",
Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Exploring Energy Efficiency of Lightweight Block Ciphers",
(IACR) Cryptology ePrint Archive, vol. 2015, 09/2015.
"A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints",
IEEE Transactions on Circuits and Systems II, vol. 59, issue 12, pp. 947-951, 2013.
"A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints",
IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 59-II, issue 12, pp. 947-951, 02/2012.
"Fault-Tolerant Network Interfaces for Networks-on-Chip",
IEEE Trans. Dependable Secur. Comput., vol. 11, issue 1, pp. 16–29, 01/2014.
"A Framework for Disturbance Analysis in Smart Grids by Fault Injection",
Springer Journal on "Computer Science - Research and Development", 09/2016.
"Hardware Implementation of the Rijndael Sbox: a Case Study",
ST Journal of System Research, pp. 84-91, July, 2003.
"Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags",
Springer Journal of Cryptographic Engineering, vol. 1, issue 1, 2011.
"Impact of Failure Prediction on Availability: Modeling and Comparative Analysis of Predictive and Reactive Methods",
IEEE Transactions on Dependable and Secure Computing, pp. 1-1, 2018.
"An Incremental Change Detection Test Based on Density Difference Estimation",
IEEE Transactions on Systems, Man, and Cybernetics: Systems, vol. 47, pp. 2714-2726, Oct, 2017.