]
"High-Level Synthesis of Benevolent Trojans",
Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE), 2019.
"Fault attacks, injection techniques and tools for simulation",
10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015, Naples, Italy, IEEE, pp. 1-6, 04/2015.
"Fault Attacks, Injection Techniques and Tools for Simulation",
Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, First edition; 2016: Springer, pp. 149-167, 2017.
"UML System-Level Analysis and Design of Secure Communication Schemes for Embedded Systems",
FDL'04, Lille, France, pp. 301-312, September 14-17, 2004.
"Trojans in Early Design Steps - An Emerging Threat",
TRUDEVICE Final Conference (FCTRUâ16), 2016.
"Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADS) for Fluorescence Lifetime Imaging Application with Picosecond Resolution",
International Image Sensor Workshop (IISW), Snowbird Resort, Utah, USA, June, 2013.
"WAMS - an adaptive system for knowledge acquisition and decision support: the case of Scaphoideus titanus",
IOBC/WPRS European Meeting, Lacanau, France, Working Group on Integrated Protection and Production in Viticulture, pp. 57-64, 10/2011.
"Calibration and in-Field Validation Tests of a Web-based Adaptive Management System for Monitoring - Scaphoideus titanus",
Future Integrated Pest Management in Europe, 2013.
Introduction to SysML,
, April 20, 2007.
"UML-based specifications of an embedded system oriented to HW/SW partitioning: a case study",
Languages for system specification: Selected contributions on UML, systemC, system Verilog, mixed-signal systems, and property specification from FDL'03, Norwell, MA, USA, Kluwer Academic Publishers, pp. 71-84, 2004.
"Physical attacks, introduction and application to embedded processors",
10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015, Napoli, Italy, IEEE, pp. 1, 06/2015.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology",
Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures",
FDL'05 - Forum on Specification and Design Languages, Lausanne, Switzerland, September 27-30, 2005.
"Midori: (A) Block Cipher for Low Energy (Extended Version)",
(IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
"Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies",
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
"Instruction Set Extensions for secure applications",
Design, Automation Test in Europe Conference DATE 2016, Dresden, Germany, IEEE, pp. 1529-1534, 03/2016.
"Challenges in designing trustworthy cryptographic co-processors",
IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal, IEEE, pp. 2009-2012, 09/2015.
"Hardware/Software Partitioning and Interface Synthesis in Networks On Chip",
IP Based SoC Design 2005, Grenoble, France, December 7-8, 2005.
"FPGA Implementations of the AES Masked Against Power Analysis Attacks",
2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE), Darmstadt, Germany, February, 2011.
"Interface Synthesis in Multiprocessing Systems-on-Chips",
IP Based SoC Design 2004, Grenoble, December, 2004.