]
"Flexible Power Modeling for Wireless Systems: Power Modeling and Optimization of two Bluetooth Implementations",
WOWMOM '05: Proceedings of the Sixth IEEE International Symposium on a World of Wireless Mobile and Multimedia Networks (WoWMoM'05), Washington, DC, USA, IEEE Computer Society, pp. 408–416, 2005.
"FSM–based power modeling of wireless protocols: the case of bluetooth",
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design, Newport Beach, California, USA, ACM Press, New York, USA, pp. 369-374, 2004.
"Power/Performance Tradeoffs in Bluetooth Sensor Networks",
HICSS '06: Proceedings of the 39th Annual Hawaii International Conference on System Sciences, Washington, DC, USA, IEEE Computer Society, pp. 236.2, 2006.
"Secure architectures of future emerging cryptography",
International Conference on Computing Frontiers CF'16, Como, italy, ACM New York, pp. 315-322, 05/2016.
"Special Session Paper: Efficient Arithmetic for lattice-based Cryptography",
Proceedings of the CODES+ISSS 2017, 2017.
"Lattice-based cryptography: From reconfigurable hardware to ASIC",
2016 International Symposium on Integrated Circuits (ISIC): IEEE, 12/2016.
"Rapid Creation of Application Models from Bandwidth Aware Core Graphs",
Proceedings of: IP Based SoC Design 2007, Grenoble, France, December 5-6, 2007.
"A Topology Design Customization Approach for (STNoC)",
Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007)., Catania, Italy, September 24-26, 2007.
"Application-Specific Topology Design Customization for STNoC",
DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07), Lübeck, Germany, August 29-31, 2007.
"Mapping and Topology Customization Approaches for Application-Specific STNoC Designs",
IEEE Proceedings of ASAP'07 - 18th International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec, Canada, July, 2007.
"Response Surface Modeling for Embedded System Design Space Exploration",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching",
Proceedings of 15th Annual IFIP International Conference on Very Large Scale Integration {(IFIP-VLSI 07)},(best paper award), Atlanta, Georgia, USA, October 15-17, 2007.
"Particle Swarm Optimization with Discrete Recombination: An Online Optimizer for Evolvable Hardware",
1st NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2006), Istanbul, Turkey, June 16-18, 2006.
"System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, pp. 435-448, 2017.
"TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In Press.
"Black-Hat High-Level Synthesis: Myth or Reality?",
IEEE Transactions on Very Large Scale Integration Systems, In Press.
"Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis",
Advances in Parallel Computing, 2018.
"High-Level Synthesis of Benevolent Trojans",
Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE), 2019.
"TAO: Techniques for Algorithmic Obscuration during High-Level Synthesis",
Proceedings of the ACM/IEEE Design Automation Conference (DAC), 2018.
"Securing Hardware Accelerators: a New Challenge for High-Level Synthesis",
IEEE Embedded Systems Letters, vol. 3, issue 10, pp. 77-80, 11/2017, 2018.