"A Security Service Protocol for MANETs", Consumer Communications and Networking Conference. CCNC 2009, in Las Vegas, Nevada, USA, IEEE, 01/2009.
"Semi-Automated HW/SW Co-design for Embedded Systems: from MARTE Models to SystemC Simulators", FDL'09 Proceedings, Sophia-Antipolis, France, September 22-24, 2009.
"Simulation of a Self-adaptive Run-time Environment with Hardware and Software Components", SINTER '09: Proceedings of the 2009 ESEC/FSE workshop on Software integration and evolution @ runtime, Amsterdam, The Netherlands, ACM, pp. 37–40, August, 2009.
"Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips", NoCArc'09: Proceedings of the Second International Workshop on Network on-Chip Architectures, New York City, USA, pp. 37–42, December, 2009.
"A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm", SECRYPT, Porto, Portugal, July 26, 2008.
"An adaptable FPGA-based System for Regular Expression Matching", Proceedings of Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, March 10-14, 2008.
"An Automated Design Flow for NoC-based MPSoCs on FPGA", RSP 2008, The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, Monterey, USA/CA, June 2-5, 2008.
"Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?", Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), October 1-3, 2008.
"Code Generation from Statecharts: Simulation of Wireless Sensor Networks", Proceedings of DSD08, Parma, Italy, September, 2008.
"An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks", Proc. IFIP International Conference on Very Large Scale Integration VLSI - SoC 2008, Rhodes Island, Greece, October 13-15, 2008.
"An Enhanced Service Provider Communication Interface with Client Priorization", proceedings of IEEE/WFMC International Conference on e-Business, July 26-29, 2008.
"Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities", Proceedings of MARTE Workshop (DATE08), Munich, Germany, March, 2008.
Hardware scheduled SMP architectures, , no. US 11/947,278, 06/2008.
"Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoCs", Proceedings of the 21st IPDPS 2007 Reconfigurable Architecture Workshop (RAW), 21th IEEE International Parallel and Distributed Processing Symposium, Miami, USA/FL, April, 2008.
"Model-based Design Space Exploration for RTES with SysML and MARTE", Proceedings of FDL08, Stuttgart, Germany, September, 2008.
"Modelling the Power Cost of Security in Wireless Sensor Networks : the Case of 802.15.4", Proceedings of IEEE ICT08, Saint Petersburg, Russia, June, 2008.
"A Protocol For Pervasive Distributed Computing Reliability", SecPri_WiMob 2008, Avignon, France, IEEE, 10/2008.
"Secure Memory Accesses on Networks-on-Chip", IEEE Transactions on Computers, vol. 57, no. 9, pp. 1216-1229, September, 2008.
"A Security Monitoring Service for NoCs", Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'08), Atlanta, Georgia, USA., 10/2008.
"Application-Specific Topology Design Customization for STNoC", DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07), Lübeck, Germany, August 29-31, 2007.