]
"An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks",
Proc. IFIP International Conference on Very Large Scale Integration VLSI - SoC 2008, Rhodes Island, Greece, October 13-15, 2008.
"ARTE: an Application-specific Run-Time Management Framework for Multi-cores based on Queuing Models",
Parallel Computing, 2013.
"Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures",
Proc. Design, Automation Test in Europe Conf. Exhibition (DATE), March, 2012.
"Design-space Exploration and Runtime Resource Management for Multicores",
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors, vol. 13, issue 2, pp. 20:1–20:27, 09/2013.
"Multicube Explorer - A Design Space Exploration Framework for Embedded Systems-on-Chip",
Proceedings of the DATE'09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Nice, France, April, 2009.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems",
Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
"Fresh Re-Keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices",
Proceedings of Progress in Cryptology - Africacrypt, Stellenbosch, South Africa, May, 2010.
"Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks",
10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
"System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach",
Proceedings of the 15th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'12), Izmir, Turkey, September 5-8, 2012.
Reconfigurable Logic Circuit,
, no. GB1719355.8, 11/2017, Submitted.
"Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow",
Proceedings of FCCM, 05/2018.
"NPART - node placement algorithm for realistic topologies in wireless multihop network simulation",
Proceedings of the 2nd International Conference on Simulation Tools and Techniques, ICST, Brussels, Belgium, Belgium, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), 2009.
"Trojan Families Identification Using Dynamic Features and Low Complexity Classifiers",
24th EICAR Annual Conference 2016 "Trustworthiness in IT Security Products", Nuremberg, Germany, EICAR, 10/2016.
"Malware Threats and Solutions for Trustworthy Mobile Systems Design",
Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, First edition; 2016: Springer, pp. 149-167, 2017.
"Security Challenges for Hardware Designers of Mobile Systems",
2015 Mobile Systems Technologies Workshop (MST), May, 2015.
"A Friend or a Foe? Detecting Malware Using Memory and CPU Features",
SECRYPT 2016, 13th International Conference on Security and Cryptography, Lisbon, Portugal, SciTePress Digital Library, 07/2016.
"Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach",
41st Computing in Cardiology Conference (CinC), Cambridge, MA, USA, IEEE Computer Society, 09/2014.
"What Does the Memory Say? Towards the most indicative features for efficient malware detection",
CCNC 2016, The 13th Annual IEEE Consumer Communications & Networking Conference, Las Vegas, NV, USA, IEEE Communication Society, 01/2016.
"MalAware: Effective and Efficient Run-time Mobile Malware Detector",
The 14th IEEE International Conference on Dependable, Autonomic and Secure Computing (DASC 2016), Auckland, New Zealand, IEEE Computer Society Press, 08/2016.
"Can we Achieve both Privacy Protection and Efficient Malware Detection on Smartphones?",
1st Interdisciplinary Cyber Research Workshop 2015, Tallin, Estona, Tallinn University of Technology, 07/2015.