]
"An industrial design space exploration framework for supporting run-time resource management on multi-core systems",
Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.
"Design Space Exploration of a Reconfigurable System for Supporting Video Streaming Run-time Management",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction",
23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, IEEE, 09/2013.
"Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip",
Euromicro Proceedings of DSD'09 - Conference on Digital System Design, Patras, Greece, August, 2009.
"An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks",
Proc. IFIP International Conference on Very Large Scale Integration VLSI - SoC 2008, Rhodes Island, Greece, October 13-15, 2008.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems",
Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
"Fresh Re-Keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices",
Proceedings of Progress in Cryptology - Africacrypt, Stellenbosch, South Africa, May, 2010.
"Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks",
10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
"System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach",
Proceedings of the 15th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'12), Izmir, Turkey, September 5-8, 2012.
"Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow",
Proceedings of FCCM, 05/2018.
Reconfigurable Logic Circuit,
, no. GB1719355.8, 11/2017, Submitted.
"NPART - node placement algorithm for realistic topologies in wireless multihop network simulation",
Proceedings of the 2nd International Conference on Simulation Tools and Techniques, ICST, Brussels, Belgium, Belgium, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), 2009.
"A Resource-optimized Approach to Efficient Early Detection of Mobile Malware",
3rd International Workshop on Security of Mobile Applications - IWSMA 2014, Fribourg, Switzerland, 09/2014.
"MalAware: Effective and Efficient Run-time Mobile Malware Detector",
The 14th IEEE International Conference on Dependable, Autonomic and Secure Computing (DASC 2016), Auckland, New Zealand, IEEE Computer Society Press, 08/2016.
"A General Practitioner or a Specialist for Your Infected Smartphone?",
36th IEEE Symposium on Security and Privacy , San Jose, CA, USA, IEEE Computer Society Technical Committee on Security and Privacy, 05/2015.
"Time, Accuracy and Power Consumption Tradeoff in Mobile Malware Detection Systems",
Computers & Security, vol. 82, pp. 314-328, 05/2019.
"Security Challenges for Hardware Designers of Mobile Systems",
2015 Mobile Systems Technologies Workshop (MST), May, 2015.
"Runtime Classification of Mobile Malware for Resource-constrained Devices",
Lecture Notes in Communications in Computer and Information Science, vol. 764: Springer International Publishing AG, pp. 195-215, 2017.
"Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach",
41st Computing in Cardiology Conference (CinC), Cambridge, MA, USA, IEEE Computer Society, 09/2014.
"What Does the Memory Say? Towards the most indicative features for efficient malware detection",
CCNC 2016, The 13th Annual IEEE Consumer Communications & Networking Conference, Las Vegas, NV, USA, IEEE Communication Society, 01/2016.