Export 140 results:
Author Title Type [ Year
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"Mapping and Topology Customization Approaches for Application-Specific STNoC Designs",
IEEE Proceedings of ASAP'07 - 18th International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec, Canada, July, 2007.
"Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits",
proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
"Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach",
Proceedings of CCNC 2007, Las Vegas, USA, January 11-13, 2007.
"A Query Unit for the IPSec Databases",
SECRYPT 2007, Barcelona, Spain, 07/2007.
"ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching",
Proceedings of 15th Annual IFIP International Conference on Very Large Scale Integration {(IFIP-VLSI 07)},(best paper award), Atlanta, Georgia, USA, October 15-17, 2007.
"SC2: State Charts to System C: Automatic Executable Models Generation",
proceedings FDL07, Barcelona, Spain, September, 2007.
"Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies",
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
"Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies",
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
"Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies",
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
"StateCharts to SystemC: a High Level Hardware Simulation Approach",
Proceedings of GLSVLSI 2007, Stresa, Italy, March 11-13, 2007.
"A Topology Design Customization Approach for (STNoC)",
Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007)., Catania, Italy, September 24-26, 2007.
"An adaptable FPGA-based System for Regular Expression Matching",
Proceedings of Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, March 10-14, 2008.
"An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks",
Proc. IFIP International Conference on Very Large Scale Integration VLSI - SoC 2008, Rhodes Island, Greece, October 13-15, 2008.
"An Enhanced Service Provider Communication Interface with Client Priorization",
proceedings of IEEE/WFMC International Conference on e-Business, July 26-29, 2008.
"Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities",
Proceedings of MARTE Workshop (DATE08), Munich, Germany, March, 2008.
"Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities",
Proceedings of MARTE Workshop (DATE08), Munich, Germany, March, 2008.
"Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoCs",
Proceedings of the 21st IPDPS 2007 Reconfigurable Architecture Workshop (RAW), 21th IEEE International Parallel and Distributed Processing Symposium, Miami, USA/FL, April, 2008.
"Model-based Design Space Exploration for RTES with SysML and MARTE",
Proceedings of FDL08, Stuttgart, Germany, September, 2008.
"A Protocol For Pervasive Distributed Computing Reliability",
SecPri_WiMob 2008, Avignon, France, IEEE, 10/2008.
"Secure Memory Accesses on Networks-on-Chip",
IEEE Transactions on Computers, vol. 57, no. 9, pp. 1216-1229, September, 2008.