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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Author Title [ Type(Asc)] Year
Journal Article
Bo, L., C. Alippi, and D. Zhao, "A Pdf-free Change Detection Test Based on Density Difference Estimation", IEEE Transactions on Neural Networks and Learning Systems, vol. 29, issue 2, pp. 324 - 334, 11/2016, 2018.
Mariani, G., G. Palermo, C. Silvano, and V. Zaccaria, "OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Space", IEEE Transactions on Computer-Aided Design, vol. 21, issue 5, no. -: IEEE, pp. 740-753, 05/2012.
Livi, L., and C. Alippi, "One-class classifiers based on entropic spanning graphs", IEEE Transactions on Neural Networks and Learning Systems, vol. 28, issue 12, pp. 2846 - 2858, 11/2016, 2017.
Alippi, C., and M. Roveri, "The (Not) Far-Away Path to Smart Cyber-Physical Systems: An Information-Centric Framework", Computer, vol. 50, pp. 38-47, April, 2017.
Bianchi, F. Maria, L. Livi, C. Alippi, and R. Jenssen, "Multiplex visibility graphs to investigate recurrent neural network dynamics", Nature-Scientific reports, vol. 7, pp. 44037-44049, 03/2017.
Alippi, C., S. Ntalampiras, and M. Roveri, "Model-Free Fault Detection and Isolation in Large-Scale Cyber-Physical Systems", IEEE Transactions on Emerging Topics in Computational Intelligence, vol. 1, pp. 61-71, Feb, 2017.
Regazzoni, F., S. Banik, A. Bogdanov, T. Isobe, K. Shibutani, H. Hiwatari, and T. Akishita, "Midori: (A) Block Cipher for Low Energy (Extended Version)", (IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
Derin, O., E. Diken, and L. Fiorin, "A Middleware Approach to Achieving Fault-tolerance of Kahn Process Networks on Networks-on-Chips", International Journal of Reconfigurable Computing, vol. 2011, no. Article ID 295385: Hindawi, pp. 14 pages, February, 2011.
Ykman-Couvreur, C., P. Avasare, G. Mariani, V. Zaccaria, G. Palermo, and C. Silvano, "Linking run-time resource management of embedded multi-core platforms with automated design-time exploration", IET Computers and Digital Techniques, vol. 5, no. -, pp. 123–135, 2011.
Zhao, D., L. Bu, C. Alippi, and Q. Wei, "A Kolmogorov-Smirnov Test to Detect Changes in Stationarity in Big Data", IFAC-PapersOnLine, vol. 50, pp. 14260 - 14265, 2017.
Brannigan, S., N. Smyth, T. Oder, F. Valencia, E. O'Sullivan, T. Güneysu, and F. Regazzoni, "An Investigation of Sources of Randomness Within Discrete Gaussian Sampling", IACR Cryptology ePrint Archive, vol. 2017, pp. 298, 2017.
Bianchi, F. Maria, L. Livi, and C. Alippi, "Investigating echo state networks dynamics by means of recurrence analysis", IEEE Transactions on Neural Networks and Learning Systems, vol. 29, pp. 427 - 439, 02/2018.
Bu, L., D. Zhao, and C. Alippi, "An Incremental Change Detection Test Based on Density Difference Estimation", IEEE Transactions on Systems, Man, and Cybernetics: Systems, vol. 47, pp. 2714-2726, Oct, 2017.
Kaitović, I., and M. Malek, "Impact of Failure Prediction on Availability: Modeling and Comparative Analysis of Predictive and Reactive Methods", IEEE Transactions on Dependable and Secure Computing, pp. 1-1, 2018.
Hocquet, C., D. Kamel, F. Regazzoni, J-D. Legat, D. Flandre, D. Bol, and F-X. Standaert, "Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags", Springer Journal of Cryptographic Engineering, vol. 1, issue 1, 2011.
Macchetti, M., and G M. Bertoni, "Hardware Implementation of the Rijndael Sbox: a Case Study", ST Journal of System Research, pp. 84-91, July, 2003.
Kaitović, I., F. Obradović, S. Luković, and M. Malek, "A Framework for Disturbance Analysis in Smart Grids by Fault Injection", Springer Journal on "Computer Science - Research and Development", 09/2016.
Fiorin, L., and M. Sami, "Fault-Tolerant Network Interfaces for Networks-on-Chip", IEEE Trans. Dependable Secur. Comput., vol. 11, issue 1, pp. 16–29, 01/2014.
Bol, D., C. Hocquet, and F. Regazzoni, "A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints", IEEE Transactions on Circuits and Systems II, vol. 59, issue 12, pp. 947-951, 2013.
Bol, D., C. Hocquet, and F. Regazzoni, "A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints", IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 59-II, issue 12, pp. 947-951, 02/2012.

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