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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Filters: First Letter Of Title is S and Author is Francesco Regazzoni  [Clear All Filters]
2018
Chaves, R., Ł. Chmielewski, F. Regazzoni, and L. Batina, "SCA-Resistance for AES: How Cheap Can We Go?", Progress in Cryptology – AFRICACRYPT 2018, Cham, Springer International Publishing, 2018.
Pilato, C., S. Garg, R. Karri, and F. Regazzoni, "Securing Hardware Accelerators: a New Challenge for High-Level Synthesis", IEEE Embedded Systems Letters, vol. 3, issue 10, pp. 77-80, 11/2017, 2018.
Regazzoni, F., C. Alippi, and I. Polian, "Security: The Dark Side of Approximate Computing?", Proceedings of the International Conference on Computer-Aided Design, New York, NY, USA, ACM, 11/2018.
2016
O'Neill, M., E. O'Sullivan, G. McWilliams, M-J. Saarinen, C. Moore, A. Khalid, J. Howe, R. Del Pino, M. Abdalla, F. Regazzoni, et al., "Secure architectures of future emerging cryptography", International Conference on Computing Frontiers CF'16, Como, italy, ACM New York, pp. 315-322, 05/2016.
Howe, J., C. Moore, M. O'Neill, F. Regazzoni, T. Güneysu, and K.. Beeden, "Standard lattices in hardware", Proceedings of the 53rd Annual Design Automation Conference DAC 2016, Austin, TX, USA, ACM, pp. 162, 06/2016.
2015
Milosevic, J., A. Ferrante, and F. Regazzoni, "Security Challenges for Hardware Designers of Mobile Systems", 2015 Mobile Systems Technologies Workshop (MST), May, 2015.
Guo, X., N. Karimi, F. Regazzoni, C. Jin, and R. Karri, "Simulation and Analysis of Negative-Bias Temperature Instability Aging on Power Analysis Attacks", IEEE Int. Symposium on Hardware-Oriented Security and Trust, McLean, VA, USA, 05/2015.
Bhasin, S., and F. Regazzoni, "A survey on hardware trojan detection techniques", IEEE International Symposium on Circuits and Systems (ISCAS) 2015, 2015, Lisbon, Portugal, IEEE, pp. 2021-2024, 08/2015.
2014
Durvaux, F., S. Kerckhof, F. Regazzoni, and F-X. Standaert, "Security IPs and IP Security with FPGAs", Secure Smart Embedded Devices Platform and Applications, 2014.
Barenghi, A., G. Pelosi, and F. Regazzoni, "Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks", (IACR) Cryptology ePrint Archive, vol. 2014, 05/2014.
Regazzoni, F., S. Burri, D. Stucki, Y. Maruyama, C. Bruschini, and E. Charbon, "Single-Photon Avalanche Diodes (SPADs) for quantum random number generators and beyond", 19th Asia and South Pacific Design Automation Conference (ASP-DAC) 2014, Singapore, IEEE, 01/2014.
Becker, G., F. Regazzoni, C. Paar, and W. Burleson, "Stealthy Dopant-Level Hardware Trojans: Extended Version", Journal of Cryptographic Engineering, vol. 4, issue 1, pp. 19-31, 04/2014.
2013
Charbon, E., and F. Regazzoni, "Single-Photon Image Sensors", Special Session, 50th Design Automation Conference (DAC), Austin, Texas, USA, June, 2013.
Bayrak, A. Galip, F. Regazzoni, D. Novo Bruna, and P. Ienne, "Sleuth: Automated Verification of Software Power Analysis Countermeasures", Workshop on Cryptographic Hardware and Embedded Systems (CHES), Santa Barbara, California, USA, August, 2013.
Becker, G., F. Regazzoni, C. Paar, and W. Burleson, "Stealthy Dopant-Level Hardware Trojans", Workshop on Cryptographic Hardware and Embedded Systems (CHES), Santa Barbara, California, USA, August, 2013.
2012
Fiorin, L., A. Ferrante, K. Padarnitsas, and F. Regazzoni, "Security Enhanced Linux on Embedded Systems: a Hardware-accelerated Implementation", 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, 02/2012.
Barenghi, A., G. Pelosi, and F. Regazzoni, "Simulation-Time Security Margin Assessment against power-based Side Channel Attacks", 7th Workshop on Embedded Systems Security (WESS), Tampere, Finland, October, 2012.
2007
Regazzoni, F., S. Badel, T. Eisenbarth, J. Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, L. Pozzi, C. Paar, Y. Leblebici, et al., "Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies", International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
2006
Bertoni, G M., L. Breveglieri, R. Farina, and F. Regazzoni, "Speeding Up AES By Extending a 32 bit Processor Instruction Set", ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), Washington, DC, USA, IEEE Computer Society, pp. 275-282, 2006.

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