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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Book Chapter
Palermo, G., C. Silvano, V. Zaccaria, E. Rigoni, C. Kavka, A. Turco, and G. Mariani, "Response Surface Modeling for Embedded System Design Space Exploration", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
Milosevic, J., M. Malek, and A. Ferrante, "Runtime Classification of Mobile Malware for Resource-constrained Devices", Lecture Notes in Communications in Computer and Information Science, vol. 764: Springer International Publishing AG, pp. 195-215, 2017.
Conference Paper
Otero, J., F. Regazzoni, and M. Lajolo, "Rapid Creation of Application Models from Bandwidth Aware Core Graphs", Proceedings of: IP Based SoC Design 2007, Grenoble, France, December 5-6, 2007.
Tumeo, A., F. Regazzoni, G. Palermo, F. Ferrandi, and D. Sciuto, "A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation", Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.
Paolieri, M., I. Bonesana, and M D. Santambrogio, "ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching", Proceedings of 15th Annual IFIP International Conference on Very Large Scale Integration {(IFIP-VLSI 07)},(best paper award), Atlanta, Georgia, USA, October 15-17, 2007.
Upasani, G., A. Calimera, A. Macii, E. Macii, and M. Poncino, "Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering", Proceedings of the 19th international workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009), Delft, The Netherlands, September 9-11, 2009.
Salvioni, C., and A V. Taddeo, "Remote Cooperation on Project-centred Learning: a Working Implemented Solution in Academia", COOPER Workshop in conjunction with EC-TEL07 Conference, September 17, 2007.
Milosevic, J., A. Dittrich, A. Ferrante, and M. Malek, "A Resource-optimized Approach to Efficient Early Detection of Mobile Malware", 3rd International Workshop on Security of Mobile Applications - IWSMA 2014, Fribourg, Switzerland, 09/2014.
Dittrich, A., D. Solis Herrera, P. Coto, and M. Malek, "Responsiveness of Service Discovery in Wireless Mesh Networks", 20th Pacific Rim International Symposium on Dependable Computing (PRDC), Singapore, IEEE Computer Society, 11/2014.
Mentens, N., E. Charbon, and F. Regazzoni, "Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow", Proceedings of FCCM, 05/2018.
Milosevic, J., A. Dittrich, A. Ferrante, M. Malek, C. Rojas Quiros, R. Braojos, G. Ansaloni, and D. Atienza, "Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach", 41st Computing in Cardiology Conference (CinC), Cambridge, MA, USA, IEEE Computer Society, 09/2014.
Bozzon, A., T. Iofciu, W. Nejdl, A V. Taddeo, and S. Tonnies, "Role Based Access Control for the interaction with Search Engines", COOPER Workshop in conjunction with EC-TEL07 Conference, September 17, 2007.
Banik, S., A. Bogdanov, F. Regazzoni, T. Isobe, H. Hiwatari, and T. Akishita, "Round gating for low energy block ciphers", 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST, McLean, VA, USA, IEEE Computer Society, pp. 55-60, 05/2016.
Mariani, G., V-M. Sima, G. Palermo, V. Zaccaria, G. Marchiori, C. Silvano, and K. Bertels, "Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction", 23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, IEEE, 09/2013.
Taddeo, A V., and A. Ferrante, "Run-time Selection of Security Algorithms For Networked Devices", 5th ACM International Symposium on QoS and Security for Wireless and Mobile Networks, Tenerife, Canary Islands, Spain, 2009.
Patent
Mentens, N., E. Charbon, and F. Regazzoni, Reconfigurable Logic Circuit, , no. GB1719355.8, 11/2017, Submitted.