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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Filters: Keyword is unified modeling language (UML)  [Clear All Filters]
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B
Basu, A S., M. Lajolo, and M. Prevostini, "A Methodology for Bridging the Gap between UML and Codesign", UML for SOC Design, Dordrecht, The Netherlands, Springer, pp. 119-146, 2005.
Basu, A S., M. Lajolo, and M. Prevostini, "UML in an Electronic System Level Design Methodology", UML-SOC'04, San Diego, California, pp. 47-52, June 6, 2004.
Basu, A S., M. Lajolo, and M. Prevostini, "Design and Synthesis of Reusable Platforms with Programmable Interconnects", UML-SoC 2005, Anaheim, California, pp. 43-48, June 12, 2005.
Boiko, U., A. Ferrante, A. Lo Duca, and V. Piuri, "A Methodology for Testing IPSec-based Systems", SoftCOM 2004, Split, pp. 22-26, October, 2004.
L
Lajolo, M., A S. Basu, and M. Prevostini, "UML Specifications Towards a Codesign Environment", FDL'04, Lille, France, pp. 313-324, September 14-17, 2004.
Luković, S., I. Kaitović, M. Mura, and U. Bondi, "Virtual Power Plant as a bridge between Distributed Energy Resources and Smart Grid", Proceedings of 43th Hawaii International Conference on System Sciences (HICSS'43), Hawaii, USA, January, 2010.
Luković, S., I. Kaitović, M. Mura, U. Bondi, F. Kulić, and D. Popović, "Functional model of Virtual Power Plant (VPP)", Proceedings of the 2010 CIGRE (International Council on Large Electric Systems) Session, Paris, France, July, 2010.
M
Minosi, A., A. Martinola, S. Mankan, and M. Prevostini, "System-level design of embedded applications by UML: the Wireless Meter Reading case", MSy2002 Workshop, Winterthur, pp. 181-187, October 3-4, 2002.
Minosi, A., S. Mankan, A. Martinola, F. Balzarini, A N. Kostadinov, and M. Prevostini, "UML-based Specifications of an Embedded System Oriented to HW/SW Partitioning: a Case Study", FDL'03, Frankfurt, pp. 226-237, September 23-26, 2003.
Mura, M., and M. Paolieri, "SC2: State Charts to System C: Automatic Executable Models Generation", proceedings FDL07, Barcelona, Spain, September, 2007.
Mura, M., L G. Murillo, and M. Prevostini, "Model-based Design Space Exploration for RTES with SysML and MARTE", Proceedings of FDL08, Stuttgart, Germany, September, 2008.
Mura, M., A. Panda, and M. Prevostini, "Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities", Proceedings of MARTE Workshop (DATE08), Munich, Germany, March, 2008.
Mura, M., M. Paolieri, L. Negri, and M. Sami, "StateCharts to SystemC: a High Level Hardware Simulation Approach", Proceedings of GLSVLSI 2007, Stresa, Italy, March 11-13, 2007.
P
Piscopo, G., M. Prevostini, and I. Stefanini, "UML System-Level Analysis and Design of Secure Communication Schemes for Embedded Systems", FDL'04, Lille, France, pp. 301-312, September 14-17, 2004.
Prevostini, M., F. Balzarini, A N. Kostadinov, S. Mankan, A. Martinola, and A. Minosi, "UML-based specifications of an embedded system oriented to HW/SW partitioning: a case study", Languages for system specification: Selected contributions on UML, systemC, system Verilog, mixed-signal systems, and property specification from FDL'03, Norwell, MA, USA, Kluwer Academic Publishers, pp. 71-84, 2004.