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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Filters: Keyword is system-on-chip (SoC)  [Clear All Filters]
Fiorin, L., L. Micconi, and M. Sami, "Design of Fault Tolerant Network Interfaces for NoCs", Proceedings of 14th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'11), Oulu, Finland, September, 2011.
Cannella, E., L. Di Gregorio, L. Fiorin, M. Lindwer, P. Meloni, O. Neugebauer, and A. Pimentel, "Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?", Embedded Systems for Real-Time Multimedia (ESTIMedia), 2011 9th IEEE Symposium on, 2011.
Fiorin, L., G. Palermo, and C. Silvano, "A Monitoring System for NoCs", Proceedings of the Third International Workshop on Network on Chip Architectures (NoCArc'2010), Atlanta, Georgia, USA, December, 2010.
Mariani, G., G. Palermo, V. Zaccaria, and C. Silvano, "An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks", Proc. IFIP International Conference on Very Large Scale Integration VLSI - SoC 2008, Rhodes Island, Greece, October 13-15, 2008.
Ferrante, A., and V. Piuri, "High-level Architecture of an IPSec-dedicated System on Chip", proceedings of NGI 2007, Trondheim, Norway, IEEE Press, May, 2007.
Dadda, L., A. Ferrante, and M. Macchetti, "A Memory Unit for Priority Management in IPSec Accelerators", proceedings of ICC07. Glasgow, Scotland: IEEE Communications Society, Glasgow, Scotland, June 24, 2007.
Ferrante, A., S. Chandra, and V. Piuri, "A Query Unit for the IPSec Databases", SECRYPT 2007, Barcelona, Spain, 07/2007.
Chandra, S., F. Regazzoni, and M. Lajolo, "Hardware/software partitioning of operating systems: a behavioral synthesis approach", GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI, Philadelphia, PA, USA, ACM Press, New York, USA, pp. 324–329, 2006.
Regazzoni, F., A C. Nacul, and M. Lajolo, "Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures", FDL'05 - Forum on Specification and Design Languages, Lausanne, Switzerland, September 27-30, 2005.
Basu, A S., M. Lajolo, and M. Prevostini, "Design and Synthesis of Reusable Platforms with Programmable Interconnects", UML-SoC 2005, Anaheim, California, pp. 43-48, June 12, 2005.
Regazzoni, F., and M. Lajolo, "Hardware/Software Partitioning and Interface Synthesis in Networks On Chip", IP Based SoC Design 2005, Grenoble, France, December 7-8, 2005.
Regazzoni, F., and M. Lajolo, "Interface Synthesis in Multiprocessing Systems-on-Chips", IP Based SoC Design 2004, Grenoble, December, 2004.
Basu, A S., M. Lajolo, and M. Prevostini, "UML in an Electronic System Level Design Methodology", UML-SOC'04, San Diego, California, pp. 47-52, June 6, 2004.
Lajolo, M., A S. Basu, and M. Prevostini, "UML Specifications Towards a Codesign Environment", FDL'04, Lille, France, pp. 313-324, September 14-17, 2004.