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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Author Title [ Type(Desc)] Year
Filters: Keyword is cryptography  [Clear All Filters]
Conference Paper
Bertoni, G M., L. Breveglieri, R. Farina, and F. Regazzoni, "A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm", SECRYPT, Porto, Portugal, July 26, 2008.
Regazzoni, F., R. Graves, G. Di Natale, L. Batina, S. Bhasin, B. Ege, A. P. Fournaris, N. Mentens, S. Picek, V. Rozic, et al., "Challenges in designing trustworthy cryptographic co-processors", IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal, IEEE, pp. 2009-2012, 09/2015.
Banik, S., A. Bogdanov, and F. Regazzoni, "Exploring the energy consumption of lightweight blockciphers in FPGA", International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, 2015, Rivera Maya, Mexico City, IEEE, pp. 1-6, 02/2016, 2015.
Regazzoni, F., "Physical attacks, introduction and application to embedded processors", 10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015, Napoli, Italy, IEEE, pp. 1, 06/2015.
Regazzoni, F., T. Eisenbarth, J. Großschädl, L. Breveglieri, P. Ienne, I. Koren, and C. Paar, "Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits", proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
Milosevic, J., A. Ferrante, and F. Regazzoni, "Security Challenges for Hardware Designers of Mobile Systems", 2015 Mobile Systems Technologies Workshop (MST), May, 2015.
Bertoni, G M., L. Breveglieri, R. Farina, and F. Regazzoni, "Speeding Up AES By Extending a 32 bit Processor Instruction Set", ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), Washington, DC, USA, IEEE Computer Society, pp. 275-282, 2006.
Journal Article
Bayrak, A. Galip, F. Regazzoni, D. Novo, P. Brisk, F-X. Standaert, and P. Ienne, "Automatic Application of Power Analysis Countermeasures", IEEE Transactions on Computers , vol. 64, issue 2, pp. 329-341, 02/2015.