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"Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes",
International Conference on VLSI Design & Embedded Systems, Bangalore, India, January 6-10, 2007.
"Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits",
proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
"Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies",
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.