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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleTowards a Reliability-aware Design Flow for Kahn Process Networks on NoC-based Multiprocessors
Publication TypeBook Chapter
Year of Publication2014
AuthorsDerin, O., and L. Fiorin
Book Title10th Workshop on Dependability and Fault Tolerance (ARCS/VERFE'14)
Series TitleLecture Notes on Computer Science
CityL├╝beck, Germany
Keywordsfault tolerance, kahn process networks (KPN), networks-on-chip (NoC), reliability

In order to satisfy performance and low power requirements of applications, embedded systems are becoming increasingly complex and highly integrated with various types of cores. As complexity increases and CMOS technology scales down into the deep-submicron domain, the rate of hard and soft faults in such systems increases. Such trend requires the reliability aspect to be incorporated as a design goal along with the more conventional goals such as performance, cost and power. In this paper, we investigate the reliability achieved by two system-level fault tolerance techniques, namely online task remapping and N-modular redundancy. By means of an analytical model of applications represented as Kahn Process Networks running on heterogeneous multiprocessors based on Networks-on-Chip, we evaluate these techniques with respect to the obtained level of reliability (mean-time-to-failure) and the overhead in computation (execution time) and communication (amount of data transfer on the network). By presenting a reliability estimation method, we enable a reliability-aware design flow on NoC-based MPSoCs.