|Title||Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering|
|Publication Type||Conference Paper|
|Year of Publication||2009|
|Authors||Upasani, G., A. Calimera, A. Macii, E. Macii, and M. Poncino|
|Conference Name||Proceedings of the 19th international workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009)|
|Date Published||September 9-11|
|Conference Location||Delft, The Netherlands|
Clock-gating and power-gating have proven to be two of the most effective techniques for reducing dynamic and leakage power, respectively, in VLSI CMOS circuits. Most commercial synthesis tools do support such techniques individually, but their combined implementation is not available, since some open issues in terms of power/timing overhead associated to the control logic required for the integration are not yet solved. Moving from some recent work targeting clock-gating/power-gating integration, in this paper we present a solution for reducing the timing overhead that may occur when the integration is performed. In particular, we introduce a new, multilevel partitioning heuristic that increases the efficiency of the clustering phase, one of the key steps of our methodology. The results demonstrate the effectiveness of our solution; in fact, power-delay product and timing overhead of the circuits synthesized using the new clustering algorithm improve by 33% and 24%, respectively.