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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleRapid Creation of Application Models from Bandwidth Aware Core Graphs
Publication TypeConference Paper
Year of Publication2007
AuthorsOtero, J., F. Regazzoni, and M. Lajolo
Conference NameProceedings of: IP Based SoC Design 2007
Date PublishedDecember 5-6
Conference LocationGrenoble, France
Keywordsnetwork-on-chip (NoC), rapid prototyping
Abstract

We present a methodology that allows rapid creation of application models from bandwidth aware core graphs that are available in the literature for a wide range of applications and we discuss their applicability to the rapid exploration of multiple Networks on Chip (NoCs) layout organizations. In a bandwidth aware core graph, each node represents a core and the numbers on the edges represent the bandwidth requirements between cores. We describe core graphs in a UML object model diagram and we then have an automatic code generation tool which produces a SystemC description whose behaviour results in a packet generation on every output connection that respects the bandwidth requirements specified in the core graph. We can then rapidly derive a NoC mapping in which a specific floorplan of the cores can be evaluated and compared with alternate floorplan options for rapid design space exploration.