|Title||Model-based Design Space Exploration for RTES with SysML and MARTE|
|Publication Type||Conference Paper|
|Year of Publication||2008|
|Authors||Mura, M., L G. Murillo, and M. Prevostini|
|Conference Name||Proceedings of FDL08|
|Conference Location||Stuttgart, Germany|
|Keywords||high level design, unified modeling language (UML)|
The features of the emerging modeling languages for system design allow designers to build models of almost any kind of heterogeneous hardware-software systems, including Real Time Embedded Systems (RTES). An important goal to achieve is the implementation and use of these models in all the steps of a common design flow. One of these steps is the Design Space Exploration (DSE), which helps designers in discovering the optimal solutions among all possible combinations after mapping functional to architectural specifications; for RTES this step is particularly hard as it should include scheduling analysis in order to proof the time validity after the mapping. This paper presents some guidelines on how to use SysML and MARTE profiles to identify design points fulfilling the timing constraints of an RTES, and thus allowing to automatize DSE analysis within the system design phase.