ALaRI Hang Glider

Search form

Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleA Memory Unit for Priority Management in IPSec Accelerators
Publication TypeConference Paper
Year of Publication2007
AuthorsDadda, L., A. Ferrante, and M. Macchetti
Conference Nameproceedings of ICC07. Glasgow, Scotland: IEEE Communications Society
Date PublishedJune 24
Conference LocationGlasgow, Scotland
Keywordsaccelerator, IPSec, priority, quality of service (QoS), security, system-on-chip (SoC), SystemC
Abstract

This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support Quality of Service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed.

DOI10.1109/ICC.2007.257