|Title||High-level Architecture of an IPSec-dedicated System on Chip|
|Publication Type||Conference Paper|
|Year of Publication||2007|
|Authors||Ferrante, A., and V. Piuri|
|Conference Name||proceedings of NGI 2007|
|Conference Location||Trondheim, Norway|
|Keywords||accelerator, IPSec, priority, quality of service (QoS), security, system-on-chip (SoC), SystemC|
IPSec is a suite of protocols which adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. In this paper we propose a high level architecture of a System on Chip (SoC) which implements IPSec. This SoC has been thought to be placed on the main data path of the host machine (flow-through architecture), thus allowing for transparent processing of IPSec traffic. The functionalities of the different blocks and their interactions, along with an estimation of the internal memory size, are also shown.