@article {18552,
	title = {TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking},
	journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
	year = {In Press},
	doi = {10.1109/TCAD.2018.2834421},
	author = {Pilato, Christian and Garg, Siddharth and Wu, Kaijie and Karri, Ramesh and Regazzoni, Francesco}
}
@article {18568,
	title = {Towards Low Energy Stream Ciphers},
	journal = {IACR Transactions on Symmetric Cryptology},
	year = {In Press},
	author = {Banik, Subhadeep and Mikhalev, Vasily and Armknecht, Frederik and Isobe, Takanori and Meier, Willi and Bogdanov, Andrey and Watanabe, Yuhei and Regazzoni, Francesco}
}
@article {18594,
	title = {Time, Accuracy and Power Consumption Tradeoff in Mobile Malware Detection Systems},
	journal = {Computers \& Security},
	volume = {82},
	year = {2019},
	month = {05/2019},
	pages = {314-328},
	chapter = {314},
	issn = {01674048},
	doi = {https://doi.org/10.1016/j.cose.2019.01.001},
	author = {Milosevic, Jelena and Malek, Miroslaw and Ferrante, Alberto}
}
@conference {18555,
	title = {TAO: Techniques for Algorithmic Obscuration during High-Level Synthesis},
	booktitle = {Proceedings of the ACM/IEEE Design Automation Conference (DAC)},
	year = {2018},
	doi = {10.1145/3195970.3196126},
	author = {Pilato, Christian and Regazzoni, Francesco and Karri, Ramesh and Garg, Siddharth}
}
@conference {18530,
	title = {Time series kernel similarities for predicting Paroxysmal Atrial Fibrillation from ECGs},
	booktitle = { IJCNN 2018 : International Joint Conference on Neural Networks},
	year = {2018},
	month = {07/2018},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Rio, Brazil},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Ferrante, Alberto and Milosevic, Jelena and Malek, Miroslaw}
}
@conference {18490,
	title = {Topology Optimization of Wireless Localization Networks},
	booktitle = {European Wireless 2016 },
	year = {2016},
	month = {05/2016},
	address = {Oulu, Finland},
	abstract = {This paper addresses topology optimization problem for an ultra wide band (UWB) localization network, where trilateration is used to obtain the target position based on its distances from fixed and known anchors. Our goal is to minimize the number of anchors needed to localize a target, while keeping the localization uncertainty lower than a given threshold in an area of arbitrary shape with obstacles. Our propagation model accounts for the presence of line of sight (LOS) between nodes, while geometric dilution of precision (GDoP) is used to express the localization error introduced by trilateration. We propose two integer linear programming formulations to solve the problem. To handle the problems of large sizes, we use the greedy placement with pruning heuristic. We test our solutions through simulation and show that the integer linear programming is appropriate to handle reasonably sized problems, and the heuristic achieves the results, in terms of the number of anchors placed, within less
than 2\% of optimum on average.
},
	keywords = {localization network, propagation model, topology optimization, ultra wide band, wireless protocols, wireless sensor networks},
	author = {Bala{\'c}, Katarina and Akhmedov, Murodzhon and Prevostini, Mauro and Malek, Miroslaw}
}
@conference {18505,
	title = {Trojan Families Identification Using Dynamic Features and Low Complexity Classifiers},
	booktitle = {24th EICAR Annual Conference 2016 "Trustworthiness in IT Security Products"},
	year = {2016},
	month = {10/2016},
	publisher = {EICAR},
	organization = {EICAR},
	address = {Nuremberg, Germany},
	author = {Milosevic, Jelena and Ferrante, Alberto and Malek, Miroslaw}
}
@conference {18579,
	title = {Trojans in Early Design Steps - An Emerging Threat},
	booktitle = {TRUDEVICE Final Conference (FCTRU{\^a}16)},
	year = {2016},
	author = {Polian, Ilia and Becker, Georg and Regazzoni, Francesco}
}
@conference {18468,
	title = {(THOR) - The hardware onion router},
	booktitle = {24th International Conference on Field Programmable Logic and Applications, (FPL) 2014},
	year = {2014},
	month = {09/2014},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Munich, Germany},
	abstract = {Security and privacy of data traversing internet have always been a major concern for all users. In this context, The Onion Routing (Tor) is the most successful protocol to anonymize global Internet traffic and is widely deployed as software on many personal computers or servers. In this paper, we explore the potential of modern reconfigurable devices to efficiently realize the Tor protocol on embedded devices. In particular, this targets the acceleration of the complex cryptographic operations involved in the handshake of routing nodes and the data stream encryption. Our hardware-based implementation on the Xilinx Zynq platform outperforms previous embedded solutions by more than a factor of 9 with respect to the cryptographic handshake - ultimately enabling quite inexpensive but highly efficient routers. Hence, we consider our work as a further milestone towards the development and the dissemination of low-cost and high performance onion relays that hopefully ultimately leads again to a more private Internet.},
	keywords = {cyptographic protocol, encryption, hardware, onion routing protocol, security, THOR},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6913605},
	author = {G{\"u}neys, Tim and Regazzoni, Francesco and Sasdrich, Pascal and Wojcik, Marcin}
}
@conference {18047,
	title = {Time of Flight Error Compensation for In-Tunnel Vehicle Localization},
	booktitle = {The Fourth International Workshop on Pervasive Networks for Emergency Management, 2014 (PerNEM{\textquoteright}14)},
	year = {2014},
	month = {03/2014},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Budapest, Hungary},
	keywords = {calibration, position estimation, time of flight, vehicle localization, wireless sensor networks},
	doi = {10.1109/PerComW.2014.6815226},
	author = {Bala{\'c}, Katarina and Di Giulio, Pablo Andres and Taddeo, Antonio Vincenzo and Prevostini, Mauro}
}
@inbook {18053,
	title = {Towards a Reliability-aware Design Flow for Kahn Process Networks on NoC-based Multiprocessors},
	booktitle = {10th Workshop on Dependability and Fault Tolerance (ARCS/VERFE{\textquoteright}14)},
	series = {Lecture Notes on Computer Science},
	year = {2014},
	publisher = {Springer},
	organization = {Springer},
	address = {L{\"u}beck, Germany},
	abstract = {In order to satisfy performance and low power requirements of applications, embedded systems are becoming increasingly complex and highly integrated with various types of cores. As complexity increases and CMOS technology scales down into the deep-submicron domain, the rate of hard and soft faults in such systems increases. Such trend requires the reliability aspect to be incorporated as a design goal along with the more conventional goals such as performance, cost and power. In this paper, we investigate the reliability achieved by two system-level fault tolerance techniques, namely online task remapping and N-modular redundancy. By means of an analytical model of applications represented as Kahn Process Networks running on heterogeneous multiprocessors based on Networks-on-Chip, we evaluate these techniques with respect to the obtained level of reliability (mean-time-to-failure) and the overhead in computation (execution time) and communication (amount of data transfer on the network). By presenting a reliability estimation method, we enable a reliability-aware design flow on NoC-based MPSoCs.},
	keywords = {fault tolerance, kahn process networks (KPN), networks-on-chip (NoC), reliability},
	author = {Derin, Onur and Fiorin, Leandro}
}
@article {17738,
	title = {Towards Self-adaptive KPN Applications on NoC-based MPSoCs},
	journal = {Advances in Software Engineering},
	volume = {2012},
	year = {2012},
	month = {September},
	pages = {16 pages},
	abstract = {Self-adaptivity is the ability of a system to adapt itself dynamically to internal and external changes. Such a capability helps systems to meet the performance and quality goals, while judiciously using available resources. In this paper, we propose a framework to implement application level self-adaptation capabilities in KPN applications running on NoC-based MPSoCs. The monitor-controller-adapter mechanism is used at the application level. The monitor measures various parameters to check whether the system meets the assigned goals. The controller takes decisions to steer the system towards the goal, which are applied by the adapters. The proposed framework requires minimal modifications to the application code and offers ease of integration. It incorporates a generic adaptation controller based on fuzzy logic. We present the MJPEG encoder as a case study to demonstrate the effectiveness of the approach. Our results show that even if the parameters of the fuzzy controller are not tuned optimally, the adaptation convergence is achieved within reasonable time and error limits. Moreover, the incurred steady-state overhead due to the framework is 4\% for average frame-rate, 3.5\% for average bit-rate, and 0.5\% for additional control data introduced in the network.},
	keywords = {kahn process networks (KPN), network-on-chip (NoC), quality of service (QoS), self-adaptivity},
	doi = {http://dx.doi.org/10.1155/2012/172674},
	author = {Derin, Onur and Ramankutty, Prasanth Kuncheerat and Meloni, Paolo and Cannella, Emanuele}
}
@conference {17740,
	title = {Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?},
	booktitle = {Embedded Systems for Real-Time Multimedia (ESTIMedia), 2011 9th IEEE Symposium on},
	year = {2011},
	abstract = {The MADNESS project aims at the definition of innovative system-level design methodologies for embedded MP-SoCs, extending the classic concept of design space exploration in multi-application domains to cope with high heterogeneity, technology scaling and system reliability. The main goal of the project is to provide a framework able to guide designers and researchers to the optimal composition of embedded MPSoC architectures, according to the requirements and the features of a given target application field. The proposed approach will tackle the new challenges, related to both architecture and design methodologies, arising with the technology scaling, the system reliability and the ever-growing computational needs of modern applications. The methodologies proposed with this project act at different levels of the design flow, enhancing the state-of-the art with novel features in system-level synthesis, architectural evaluation and prototyping. Support for fault resilience and efficient adaptive runtime management is introduced at hardware and middleware level, and considered by the system-level synthesis as one of the optimization factors to be taken into account. This paper presents the first stable results obtained in the MADNESS project, already demonstrating the effectiveness of the proposed methods.},
	keywords = {adaptive MPSoC, adaptive runtime management, computer architecture, embedded MPSoC architectures, emulation, ESL design framework, fault resilience, fault tolerance, fault tolerant MPSoC, field programmable gate arrays, hardware, integrated circuit reliability, libraries, MADNESS project, middleware, multiprocessing systems, network synthesis, program processors, system level design methodologies, system level synthesis, system reliability, system-on-chip (SoC)},
	doi = {10.1109/ESTIMedia.2011.6088518},
	author = {Cannella, Emanuele and Di Gregorio, Lorenzo and Fiorin, Leandro and Lindwer, Menno and Meloni, Paolo and Neugebauer, Olaf and Pimentel, Andy}
}
@conference {125.DeDi10,
	title = {A Task-aware Middleware for Fault-tolerance and Adaptivity of Kahn Process Networks on Network-on-Chip},
	booktitle = {ReCoSoC 2010: Proceedings of the Fifth International Workshop on Reconfigurable Communication Centric System-on-Chips},
	year = {2010},
	month = {May},
	address = {Karlsruhe, Germany},
	abstract = {We propose a task-aware middleware concept and provide details for its implementation on Network-on-Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault-tolerance strategies for Kahn Process Networks (KPN) applications running on NoCs. In doing that, we extend our SACRE (Self-adaptive Component Run-time Environment) framework by integrating it with an open source NoC simulator, Noxim. We also hope that this work may help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.},
	keywords = {fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity},
	author = {Derin, Onur and Diken, Erkan}
}
@conference {118.CaVeStShCeLeAsMe10,
	title = {Trace-based KPN Composability Analysis for Mapping Simultaneous Applications to MPSoC Platforms},
	booktitle = {Proceedings of Design, Automation and Test in Europe(DATE) Conference},
	year = {2010},
	month = {March},
	address = {Dresden, Germany},
	abstract = {Nowadays, most embedded devices need to support multiple applications running concurrently. In contrast to desktop computing, very often the set of applications is known at design time and the designer needs to assure that critical applications meet their constraints in every possible use-case. In order to do this, all possible use-cases, i.e. subset of applications running simultaneously, have to be verified thoroughly. An approach to reduce the verification effort, is to perform composability analysis which has been studied for sets of applications modeled as Synchronous Dataflow Graphs. In this paper we introduce a framework that supports a more general parallel programming model based on the Kahn Process Networks Model of Computation and integrates a complete MPSoC programming environment that includes: compilercentric analysis, performance estimation, simulation as well as mapping and scheduling of multiple applications. In our solution, composability analysis is performed on parallel traces obtained by instrumenting the application code. A case study performed on three typical embedded applications, JPEG, GSM and MPEG-2, proved the applicability of our approach.},
	author = {Castrill{\'o}n, Jer{\'o}nimo and Vel{\'a}squez, Ricardo and Stulova, Anastasia and Sheng, Weihua and Ceng, Jianjiang and Leupers, Rainer and Ascheid, Gerd and Meyr, Heinrich}
}
@conference {46.ReBoDjMa07,
	title = {Tairona, an Open Source Platform for Worldwide Meeting and Tutoring},
	booktitle = {World Conference on Educational Multimedia, Hypermedia and Telecommunications 7 (ED-MEDIA 07)},
	year = {2007},
	address = {Vancouver, Canada},
	abstract = {Tairona is a web-based platform for real time meeting and tutoring. It aims to provide a solution for face to face synchronous communication between the tutor and the students in remote faculties and similar environments where a life meeting in not possible. In particular the application is tailored on needs of a scenario that is very unique: in the considered institution in fact, teachers and students meet themselves only for the week necessary to complete the course. In this paper we present the requirements that led us to design and implement Taiorna.},
	keywords = {java, learning, remote application, voice over IP (VoIP)},
	author = {Regazzoni, Francesco and Bonesana, Ivano and Djakov, Maksim and Mattiuz, Amanda}
}
@conference {66.PaMaSi07,
	title = {A Topology Design Customization Approach for (STNoC)},
	booktitle = {Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007).},
	year = {2007},
	month = {September 24-26},
	address = {Catania, Italy},
	abstract = {To support high bandwidth SoCs, a communication design flow is necessary for the design space exploration respecting tight design requirements. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a design flow for the core mapping and customization of the network topology applied to STNoC, the Network on-Chip developed by STMicroelectronics. Starting from ring topology, the proposed application-specific flow tries to find a set of customized topologies, optimized in terms of performance and area/energy overhead, by adding links. The generated STNoC custom topologies provide a reduced cost with respect to the spidergon topology.},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/ASAP.2007.4429959},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
