@conference {18588,
	title = {SCA-Resistance for AES: How Cheap Can We Go?},
	booktitle = {Progress in Cryptology {\textendash} AFRICACRYPT 2018},
	year = {2018},
	publisher = {Springer International Publishing},
	organization = {Springer International Publishing},
	address = {Cham},
	abstract = {This paper introduces a novel AES structure capable of improving the robustness against power analysis attacks while allowing for a very compact structure with a potentially negligible area and performance impact. The proposed design is based on a low entropy masking scheme, where half of the time the true value and half of the time the complemented value are used to mask the power consumption variation. The obtained experimental results suggest that the area overhead for the protection against power analysis is as low as 5{\%} LUT increase with a performance degradation of about 10{\%}. When compared with the state of the art supported on FPGAs, efficiency improvements above 6 times and a throughput improvement of at least two times higher are achieved.},
	isbn = {978-3-319-89339-6},
	author = {Chaves, Ricardo and Chmielewski, {\L}ukasz and Regazzoni, Francesco and Batina, Lejla},
	editor = {Joux, Antoine and Nitaj, Abderrahmane and Rachidi, Tajjeeddine}
}
@article {18554,
	title = {Securing Hardware Accelerators: a New Challenge for High-Level Synthesis},
	journal = {IEEE Embedded Systems Letters},
	volume = {3},
	issue = {10},
	year = {2018},
	month = {11/2017},
	pages = {77-80},
	chapter = {77},
	doi = {10.1109/LES.2017.2774800},
	author = {Pilato, Christian and Garg, Siddharth and Karri, Ramesh and Regazzoni, Francesco}
}
@conference {18584,
	title = {Security: The Dark Side of Approximate Computing?},
	booktitle = {Proceedings of the International Conference on Computer-Aided Design},
	year = {2018},
	month = {11/2018},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	isbn = {978-1-4503-5950-4},
	doi = {10.1145/3240765.3243497},
	url = {http://doi.acm.org/10.1145/3240765.3243497},
	author = {Regazzoni, Francesco and Alippi, Cesare and Polian, Ilia}
}
@article {18509,
	title = {Solving Multiobjective Optimization Problems in Unknown Dynamic Environments: An Inverse Modeling Approach},
	journal = {IEEE Transactions on Cybernetics},
	volume = {47},
	issue = {12},
	year = {2017},
	month = {11/2016},
	pages = {4223 - 4234},
	chapter = {4223},
	abstract = {Evolutionary multiobjective optimization in dynamic environments is a challenging task, as it requires the optimization algorithm converging to a time-variant Pareto optimal front. This paper proposes a dynamic multiobjective optimization algorithm which utilizes an inverse model set to guide the search towards promising decision regions. In order to reduce the number of fitness evaluations for change detection purpose, a two stage change detection test is proposed which uses the inverse model set to check potential changes in the objective function landscape. Both static and dynamic multiobjective benchmark optimization problems have been considered to evaluate the performance of the proposed algorithm. Experimental results show that the improvement in optimization performance is achievable when the proposed inverse model set is adopted.},
	doi = {10.1109/TCYB.2016.2602561},
	author = {Gee, Sen Bong and Tan, Kay Chen and Alippi, Cesare}
}
@conference {18576,
	title = {Special Session Paper: Efficient Arithmetic for lattice-based Cryptography},
	booktitle = {Proceedings of the CODES+ISSS 2017},
	year = {2017},
	author = {O{\textquoteright}Sullivan, Elizabeth and Regazzoni, Francesco}
}
@article {18550,
	title = {System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip},
	journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
	volume = {36},
	year = {2017},
	pages = {435-448},
	keywords = {algorithm design and analysis, Data structures, hardware, hardware accelerator, High-Level Synthesis, IP networks, Memory Design, Memory management, Multi-bank Architecture, Random access memory},
	doi = {10.1109/TCAD.2016.2611506},
	author = {Pilato, Christian and Mantovani, Paolo and Di Guglielmo, Giuseppe and Carloni, Luca P.}
}
@conference {18489,
	title = {Secure architectures of future emerging cryptography},
	booktitle = {International Conference on Computing Frontiers CF{\textquoteright}16},
	series = {Proceedings of the ACM International Conference on Computing Frontiers},
	year = {2016},
	month = {05/2016},
	pages = {315-322},
	publisher = {ACM New York},
	organization = {ACM New York},
	address = {Como, italy},
	abstract = {Funded under the European Union{\textquoteright}s Horizon 2020 research and innovation programme, SAFEcrypto will provide a new generation of practical, robust and physically secure post-quantum cryptographic solutions that ensure long-term security for future ICT systems, services and applications. The project will focus on the remarkably versatile field of Lattice-based cryptography as the source of computational hardness, and will deliver optimised public key security primitives for digital signatures and authentication, as well identity based encryption (IBE) and attribute based encryption (ABE). This will involve algorithmic and design optimisations, and implementations of lattice-based cryptographic schemes addressing cost, energy consumption, performance and physical robustness. As the National Institute of Standards and Technology (NIST) prepares for the transition to a post-quantum cryptographic suite B, urging organisations that build systems and infrastructures that require long-term security to consider this transition in architectural designs; the SAFEcrypto project will provide Proof-of-concept demonstrators of schemes for three practical real-world case studies with long-term security requirements, in the application areas of satellite communications, network security and cloud. The goal is to affirm Lattice-based cryptography as an effective replacement for traditional number-theoretic public-key cryptography, by demonstrating that it can address the needs of resource-constrained embedded applications, such as mobile and battery-operated devices, and of real-time high performance applications for cloud and network management infrastructures},
	keywords = {identity based encryption, lattice-based cryptography, physical attacks, public-key cryptography},
	isbn = {978-1-4503-4128-8},
	doi = {10.1145/2903150.2907756},
	url = {http://doi.acm.org/10.1145/2903150.2907756},
	author = {O{\textquoteright}Neill, Maire and O{\textquoteright}Sullivan, Elizabeth and McWilliams, Gavin and Saarinen, Markku-Juhani and Moore, Ciara and Khalid, Ayesha and Howe, James and Del Pino, Rafael and Abdalla, Michel and Regazzoni, Francesco and Valencia, Andres Felipe and G{\"u}neysu, Tim and Oder, Tobias and Waller, Adrian and Jones, Glyn and Barnett, Anthony and Griffin, Robert and Byrne, Andrew and Ammar, Bassem and Lund, David}
}
@conference {18515,
	title = {Spotting the Malicious Moment: Characterizing Malware Behavior Using Dynamic Features},
	booktitle = {2016 11th International Conference on Availability, Reliability and Security (ARES)},
	year = {2016},
	month = {08/2016},
	address = {Salzburg, Austria},
	keywords = {Android applications, Androids, automatic mobile application analysis, dynamic features, Feature extraction, Humanoid robots, informative malware identification, invasive software, learning (artificial intelligence), local malicious behavior detection, machine learning, malicious activity, malware, malware behavior characterization, malware detection tools, mobile computing, mobile devices, Mobile handsets, monitoring, pattern classification, program diagnostics, resource usage, security, system calls, user protection},
	doi = {10.1109/ARES.2016.70},
	author = {Ferrante, Alberto and Mercaldo, Francesco and Milosevic, Jelena and Visaggio, Corrado Aaron},
	editor = {Medvet, Eric}
}
@conference {18487,
	title = {Standard lattices in hardware},
	booktitle = {Proceedings of the 53rd Annual Design Automation Conference DAC 2016},
	series = {Proceedings of DAC },
	year = {2016},
	month = {06/2016},
	pages = {162},
	publisher = {ACM},
	organization = {ACM},
	address = {Austin, TX, USA},
	abstract = {Lattice-based cryptography has gained credence recently as a replacement for current public-key cryptosystems, due to its quantum-resilience, versatility, and relatively low key sizes. To date, encryption based on the learning with errors (LWE) problem has only been investigated from an ideal lattice standpoint, due to its computation and size efficiencies. However, a thorough investigation of standard lattices in practice has yet to be considered. Standard lattices may be preferred to ideal lattices due to their stronger security assumptions and less restrictive parameter selection process.

In this paper, an area-optimised hardware architecture of a standard lattice-based cryptographic scheme is proposed. The design is implemented on a FPGA and it is found that both encryption and decryption fit comfortably on a Spartan-6 FPGA. This is the first hardware architecture for standard lattice-based cryptography reported in the literature to date, and thus is a benchmark for future implementations. Additionally, a revised discrete Gaussian sampler is proposed which is the fastest of its type to date, and also is the first to investigate the cost savings of implementing with λ/2-bits of precision.

Performance results are promising compared to the hardware designs of the equivalent ring-LWE scheme, which in addition to providing stronger security proofs; generate 1272 encryptions per second and 4395 decryptions per second.
},
	keywords = {encryption, hardware design, lattice-based cryptography, physical attack},
	isbn = {978-1-4503-4236-0},
	doi = {10.1145/2897937.2898037},
	url = {http://doi.acm.org/10.1145/2897937.2898037},
	author = {Howe, James and Moore, Ciara and O{\textquoteright}Neill, Maire and Regazzoni, Francesco and G{\"u}neysu, Tim and Beeden, K.}
}
@conference {18392,
	title = {SCV2: A model-based validation and verification approach to system-of-systems engineering},
	booktitle = {System of Systems Engineering Conference (SoSE), 2015 10th},
	year = {2015},
	month = {05/2015},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Model-Based Systems Engineering provides an effective methodology for designing complex systems and System-of-Systems. More importantly, such an approach opens the possibility to automatically generate executable simulators from system modules using model-to-code transformations, in order to verify the system model{\textquoteright}s completeness and validate design requirements. However, the user may still need to write code segments to describe the detailed functionality of system components. In this paper, we present the SCV2 tool, which allows the simulation of big size heterogeneous/multiple-class systems and system-of-systems, imposes code-model consistency and aided statechart design through reverse code-to-model transformations, and provides query-based requirement validation and functionality verification through an intuitive user interface. Finally, we present a use-case showing the utilization of the tool in the WiBRATE FP7 project for early-stage validation of system requirements.},
	keywords = {Automated Code Generation, Model-based System Engineering, SoSE, StateCharts, SysML, System-of-Systems, Validation and Verification},
	doi = {10.1109/SYSOSE.2015.7151960},
	url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7151960},
	author = {Baddour, Rami and Paspaliaris, Alkiviadis and Herrera, Daniel Solis}
}
@conference {18462,
	title = {Security Challenges for Hardware Designers of Mobile Systems},
	booktitle = {2015 Mobile Systems Technologies Workshop (MST)},
	year = {2015},
	month = {May},
	keywords = {cryptographic capabilities, cryptographic primitives, cryptography, hardware, hardware design flow, hardware designers, hardware trojan, Hardware Trojans, Integrated optics, malware, mobile communication, mobile computing, mobile device, mobile devices, Mobile handsets, mobile systems, Optical device fabrication, pervasive mobile devices, physical attack, physical attacks, security, security challenges, software malware, telecommunication security, Trojan horses},
	doi = {10.1109/MST.2015.11},
	author = {Milosevic, Jelena and Ferrante, Alberto and Regazzoni, Francesco}
}
@conference {18360,
	title = {Simulation and Analysis of Negative-Bias Temperature Instability Aging on Power Analysis Attacks},
	booktitle = {IEEE Int. Symposium on Hardware-Oriented Security and Trust},
	year = {2015},
	month = {05/2015},
	address = {McLean, VA, USA},
	author = {Guo, Xiaofei and Karimi, Nagmeh and Regazzoni, Francesco and Jin, Chenglu and Karri, Ramesh}
}
@conference {18476,
	title = {A survey on hardware trojan detection techniques},
	booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS) 2015},
	year = {2015},
	month = {08/2015},
	pages = {2021-2024},
	publisher = {IEEE},
	organization = {IEEE},
	edition = {2015},
	address = {Lisbon, Portugal},
	abstract = {Hardware Trojans recently emerged as a serious issue for computer systems, especially for those used in critical applications such as medical or military. Trojan proposed so far can affect the reliability of a device in various ways. Proposed effects range from the leakage of secret information to the complete malfunctioning of the device. A crucial point for securing the overall operation of a device is to guarantee the absence of hardware Trojans. In this paper, we survey several techniques for detecting malicious modification of circuit introduced at different phases of the design flow. We also highlight their capabilities limitations in thwarting hardware Trojans.},
	keywords = {hardware Trojan detection techniques, integrated circuit reliability},
	isbn = {978-1-4799-8391-9},
	issn = {0271-4302},
	doi = {10.1109/ISCAS.2015.7169073},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7152138},
	author = {Bhasin, Shivam and Regazzoni, Francesco}
}
@inbook {18065,
	title = {Security IPs and IP Security with FPGAs},
	booktitle = {Secure Smart Embedded Devices Platform and Applications},
	year = {2014},
	author = {Durvaux, Fran{\c c}ois and Kerckhof, St{\'e}phanie and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier},
	editor = {Markantonakis, Konstantinos}
}
@article {18467,
	title = {Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks},
	journal = {(IACR) Cryptology ePrint Archive},
	volume = {2014},
	year = {2014},
	month = {05/2014},
	chapter = {307},
	abstract = {A sound design time evaluation of the security of a digital device is a goal which has attracted a great amount of research effort lately. Common security metrics for the attack consider either the theoretical leakage of the device, or assume as a security metric the number of measurements needed in order to be able to always recover the secret key. In this work we provide a combined security metric taking into account the computational effort needed to lead the attack, in combination with the quantity of measurements to be performed, and provide a practical lower bound for the security margin which can be employed by a secure hardware designer. This paper represents a first exploration of a design-time security metric incorporating the computational effort required to lead a power- based side channel attack in the security level assessment of the device. We take into account in our metric the possible presence of masking and hiding schemes, and we assume the best measurement conditions for the attacker, thus leading to a conservative estimate of the security of the device. We provide a practical validation of our security metric through an analysis of transistor-level accurate power simulations of a 128-bit AES core implemented on a 65 nm library.},
	keywords = {AES, implementation, Side-channel analysis},
	author = {Barenghi, Alessandro and Pelosi, Gerardo and Regazzoni, Francesco}
}
@conference {18470,
	title = {Single-Photon Avalanche Diodes (SPADs) for quantum random number generators and beyond},
	booktitle = {19th Asia and South Pacific Design Automation Conference (ASP-DAC) 2014},
	year = {2014},
	month = {01/2014},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Singapore},
	abstract = {Single-Photon Avalanche Diodes (SPADs) are solid-state photo-detectors capable of detecting single photons by exploiting the avalanche effect that occurs in the breakdown of a p-n junction biased above breakdown voltage. By this effect, a SPAD translates an incoming photon to a macroscopic current pulse. These devices are currently used for building medical devices characterized by a very high time resolution. An appealing application of SPAD is to use them as a basic block for building the entropy source of true random number generators. In this paper we focus on such application, and we explore the design challenges behind the realization of a quantum random number generator based on a massively parallel array of SPADs. The matrix under investigation comprises 512{\texttimes}128 independent cells that convert photons onto a raw bit-stream, which, as ensured by the properties of quantum physics, is characterized by a very high level of randomness. The sequences are read out in a 128-bit parallel bus, concatenated, and pipelined onto a de-biasing filter. Subsequently, we fabricated the proposed chip using a standard CMOS process. Our results, achieved on the manufactured device and coupling two matrices, show that our architecture can reach up to 5 Gbit/s while consuming 25pJ/bit, thus demonstrating scalability and performance for any random number generators based on SPADs},
	keywords = {quantum physics, random number generators, SPAD},
	isbn = {978-1-4799-2816-3},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6736726},
	author = {Regazzoni, Francesco and Burri, Samuel and Stucki, Damien and Maruyama, Yuki and Bruschini, Claudio and Charbon, Edoardo}
}
@conference {18251,
	title = {Smart Charging Cell for Smart Cities},
	booktitle = {The 2nd IEEE International Workshop on Intelligent Energy Systems (IWIES) },
	year = {2014},
	month = {08/2014},
	abstract = {Energy consumption can be to some extent steered not only in time but in special cases in space as well. This mostly concerns electric vehicles (EV) charging. In this work we present conceptual solution of a {\textquoteleft}GeoGreen Cell{\textquoteright} developed in scope of an international project {\textendash} Ge(o)Green. The main purpose of such an aggregation is to efficiently coordinate. EV charging with respect to price of energy both in time and space. Even though massive acceptance of EVs seems far, there is an emerging need for conceptual solutions and reference models of solutions for their seamless integration into energy system in particular in urban areas. In fact, system level models of the supporting ICT architecture, including structural and behavioral ones, have been
developed. The models have been verified by means of simulations to assure their correctness. Scheduling optimization algorithms have been created and the system has been validated by means of system-level simulations.},
	keywords = {aggregation, EV charging, structural and behavioral models, SyML},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor}
}
@article {18059,
	title = {Stealthy Dopant-Level Hardware Trojans: Extended Version},
	journal = {Journal of Cryptographic Engineering},
	volume = {4},
	issue = {1},
	year = {2014},
	month = {04/2014},
	pages = {19-31},
	abstract = {In recent years, hardware Trojans have drawn the attention of governments and industry as well as the scientific community. One of the main concerns is that integrated circuits, e.g., for military or critical-infrastructure applications, could be maliciously manipulated during the manufacturing process, which often takes place abroad. However, since there have been no reported hardware Trojans in practice yet, little is known about how such a Trojan would look like and how difficult it would be in practice to implement one. In this paper we propose an extremely stealthy approach for implementing hardware Trojans below the gate level, and we evaluate their impact on the security of the target device. Instead of adding additional circuitry to the target design, we insert our hardware Trojans by changing the dopant polarity of existing transistors. Since the modified circuit appears legitimate on all wiring layers (including all metal and polysilicon), our family of Trojans is resistant to most detection techniques, including fine-grain optical inspection and checking against {\textquotedblleft}golden chips{\textquotedblright}. We demonstrate the effectiveness of our approach by inserting Trojans into two designs{\textemdash}a digital post-processing derived from Intel{\textquoteright}s cryptographically secure RNG design used in the Ivy Bridge processors and a side-channel resistant SBox implementation{\textemdash}and by exploring their detectability and their effects on security.},
	keywords = {Hardware Trojans, Layout modifications, Malicious hardware, Trojan side-channel},
	issn = {2190-8516},
	doi = {10.1007/s13389-013-0068-0},
	author = {Becker, Georg and Regazzoni, Francesco and Paar, Christof and Burleson, Wayne}
}
@conference {17772,
	title = {A Security-enhanced Design Methodology For Embedded Systems},
	booktitle = { ICETE SECRYPT 2013},
	year = {2013},
	month = {07/2013},
	publisher = {ICETE},
	organization = {ICETE},
	address = {Reykjavik, Iceland},
	keywords = {design methodology, design space exploration, embedded systems, metric, security, security metric},
	author = {Ferrante, Alberto and Milosevic, Jelena and Janjusevic, Marija}
}
@inbook {17996,
	title = {Self-Organizing Real-Time Services in Mobile Ad Hoc Networks},
	booktitle = {Self-Organization in Embedded Real-Time Systems},
	year = {2013},
	pages = {55-74},
	publisher = {Springer New York},
	organization = {Springer New York},
	isbn = {978-1-4614-1968-6},
	doi = {10.1007/978-1-4614-1969-3_3},
	url = {http://dx.doi.org/10.1007/978-1-4614-1969-3_3},
	author = {Kakuda, Yoshiaki and Ohta, Tomoyuki and Malek, Miroslaw},
	editor = {Higuera-Toledano, Teresa and Brinkschulte, Uwe and Rettberg, Achim}
}
@conference {18070,
	title = {Single-Photon Image Sensors},
	booktitle = {Special Session, 50th Design Automation Conference (DAC)},
	year = {2013},
	month = {June},
	address = {Austin, Texas, USA},
	author = {Charbon, Edoardo and Regazzoni, Francesco}
}
@conference {18066,
	title = {Sleuth: Automated Verification of Software Power Analysis Countermeasures},
	booktitle = {Workshop on Cryptographic Hardware and Embedded Systems (CHES)},
	year = {2013},
	month = {August},
	address = {Santa Barbara, California, USA},
	author = {Bayrak, Ali Galip and Regazzoni, Francesco and Novo Bruna, David and Ienne, Paolo}
}
@conference {18039,
	title = {Smart Building Integration in Smart Grids},
	booktitle = {The 44th Heating Ventilation Air Condition and Refrigeration Congress and Exhibition - KGH 2013},
	year = {2013},
	abstract = {Modern power distribution systems gradually evolve into Smart Grids. Intelligence is getting inserted in all segments of the grid, monitoring and controlling entire power flow from generation and distribution down to consumption of home appliances. On the other hand renewable generation systems are getting widely deployed in public and residential buildings turning them into prosumers. Such scenario requires novel solutions for smart coupling of generation and consumption. Different kinds of prosumers clustering have been proposed by scientific community as a response. In the present work we propose an ICT structure capable of tackling this challenge. The conceptual solution represents an architecture which enables seamless integration of Smart Buildings into Smart Grids.},
	keywords = {Clustering, smart grid, smart home, System Level Model},
	author = {Lukovi{\'c}, Slobodan and {\v C}ongradac, Velimir and Kuli{\'c}, Filip}
}
@conference {18067,
	title = {Stealthy Dopant-Level Hardware Trojans},
	booktitle = {Workshop on Cryptographic Hardware and Embedded Systems (CHES)},
	year = {2013},
	month = {August},
	address = {Santa Barbara, California, USA},
	author = {Becker, Georg and Regazzoni, Francesco and Paar, Christof and Burleson, Wayne}
}
@conference {18054,
	title = {STRATOS: open System for TRAcTOrs{\textquoteright} autonomous OperationS},
	booktitle = {EFITA Internation Conference on Sustainable Agriculture through ICT Innovation },
	year = {2013},
	month = {06/2013},
	publisher = {European Federation for Information Technology in Agriculture, Food and the Environment},
	organization = {European Federation for Information Technology in Agriculture, Food and the Environment},
	address = {Torino, Italy},
	abstract = {This paper describes the objectives and final results of the STRATOS project (System for TRAcTOrs{\textquoteright} autonomous OperationS), within the framework of ICT-AGRI ERA-NET (Coordination of European Research within ICT and Robotics in Agriculture and related Environmental Issues). The main objective of the STRATOS project was the development of an open ICT hardware-software infrastructure enabling the acquisition of geo-referenced information on soil and terrain parameters. In more detail, STRATOS project target was to develop and demonstrate new functions enabled by ISOBUS technology (ISO 11783) that support a substantial improvement of the quality of the farming jobs. In particular the idea is to develop a technology based on ISOBUS compliant, wireless self-powered sensor network for the real time measurement of soil and harvester conditions. In this way, Task Controller (an ICT component defined by ISOBUS specification which supervises actively the farming job performed by the tractor) can optimize the whole tractor and implement operational modes to improve the farming job quality and safety of the overall systems. The project lasted from 1st April, 2011 to31st March, 2013, and this paper reports about the project achievements.},
	keywords = {agriculture, ICT, model-driven approach, precision farming, Safety},
	author = {Fantuzzi, Cesare and Gutman, Per-Olof and Kaitovi{\'c}, Igor and Larcher, Luca and Marzani, Stefano and Ruggeri, Massimiliano and Zagurskis, Valerijs}
}
@article {18050,
	title = {A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.},
	journal = {Microprocessors and Microsystems - Embedded Hardware Design},
	volume = {37},
	issue = {6-7},
	year = {2013},
	pages = {515{\textendash}529},
	doi = {10.1016/j.micpro.2013.07.007},
	author = {Derin, Onur and Cannella, Emanuele and Tuveri, Giuseppe and Meloni, Paolo and Stefanov, Todor and Fiorin, Leandro and Raffo, Luigi and Sami, Mariagiovanna}
}
@inbook {18089,
	title = {Systems Engineering for Assessment of Virtual Power System Implementations},
	booktitle = {Artificial Intelligence Applications and Innovations},
	series = {9th IFIP WG 12.5 International Conference, AIAI 2013, Paphos, Cyprus, September 30 {\textendash} October 2, 2013, Proceedings},
	volume = {412},
	year = {2013},
	pages = {667-676},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	abstract = {In this work we present an adoption of systems engineering methodology for design and assessment of a Virtual Power System (VPS). The VPS has been defined as an aggregation of distributed energy resources, consumers and storages which can operate autonomously, and is presented to the power system as a single unit in technical and commercial terms. The complexity of these critical systems is tackled by means of systems engineering. We have applied our approach in scope of a research project AlpEnergy.},
	keywords = {assessment, modeling, SysML, systems engineering, VPS},
	isbn = {978-3-642-41141-0},
	issn = {1868-4238},
	doi = {10.1007/978-3-642-41142-7_67},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor}
}
@conference {17994,
	title = {Securability: the Key Challenge for Autonomic and Trusted Computing},
	booktitle = {IEEE International Conference on Ubiquitous Intelligence Computing / International Conference on Autonomic Trusted Computing (UIC/ATC)},
	year = {2012},
	month = {03/2012},
	edition = {9},
	author = {Malek, Miroslaw}
}
@conference {17577,
	title = {Security Enhanced Linux on Embedded Systems: a Hardware-accelerated Implementation},
	booktitle = {17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012},
	year = {2012},
	month = {02/2012},
	address = {Sydney, Australia},
	abstract = {Security Enhanced Linux implements fine-grained mandatory access control. Despite its usefulness, the overhead of implementing it on embedded devices is prohibitive. Therefore, in the past it has been proposed to accelerate SELinux by means of dedicated hardware; in this work we demonstrate the feasibility of such an approach by implementing a hardware accelerator for SELinux on a FPGA-based platform. Our implementation obtains a huge reduction in the performance overhead and energy consumption of SELinux, yet employing a limited chip area.},
	keywords = {authorisation, dedicated hardware, embedded systems, energy consumption, field programmable gate arrays, fine-grained mandatory access control, FPGA-based platform, hardware accelerator, hardware-accelerated implementation, linux, performance overhead reduction, security enhanced Linux},
	doi = {10.1109/ASPDAC.2012.6164960},
	author = {Fiorin, Leandro and Ferrante, Alberto and Padarnitsas, Konstantinos and Regazzoni, Francesco}
}
@conference {18074,
	title = {Simulation-Time Security Margin Assessment against power-based Side Channel Attacks},
	booktitle = {7th Workshop on Embedded Systems Security (WESS)},
	year = {2012},
	month = {October},
	address = {Tampere, Finland},
	author = {Barenghi, Alessandro and Pelosi, Gerardo and Regazzoni, Francesco}
}
@conference {18140,
	title = {STRATOS: Open System For Tractors{\textquoteright} Autonomous Operations},
	booktitle = {5th International Conference on Automation Technology for Off-road Equipment (ATOE)},
	year = {2012},
	month = {07/2012},
	pages = {162-187},
	publisher = {International Commission of Agricultural and Biosystems Engineering (CIGR)},
	organization = {International Commission of Agricultural and Biosystems Engineering (CIGR)},
	address = {Valencia, Spain},
	abstract = {This paper describes the objectives and preliminary results of the STRATOS project (System for TRAcTOrs{\textquoteright} autonomous OperationS), within the framework of ICT-AGRI ERA-NET (Coordination of European Research within ICT and Robotics in Agriculture and related Environmental Issues). The main objective of the STRATOS project is to develop an open ICT hardware-software infrastructure enabling the partial automation of tractors and at the same time enhancing their operational safety and production efficiency, with the positive effects of reduced accident risk and environmental impact. In more detail, STRATOS project target is to develop and demonstrate new functions enabled by ISOBUS technology (ISO 11783) that support a substantial improvement of the quality of the farming jobs. In particular the idea is to develop a technology based on ISOBUS compliant, wireless self-powered sensor network for the real time measurement of soil and harvester conditions. In this way, Task Controller (an ICT component defined by ISOBUS specification which supervises actively the farming job performed by the tractor) can optimize the whole tractor and implement operational modes to improve the farming job quality and safety of the overall systems. The project started on 1 st April, 2011, and will end the 31 st March, 2013, This paper reports about some achievement gained so far.},
	keywords = {agriculture, ICT infrastructure Design, model-driven approach, precision farming, Safety},
	isbn = {84-615-9654-4},
	author = {Fantuzzi, Cesare and Gutman, Per-Olof and Kaitovi{\'c}, Igor and Larcher, Luca and Marzani, Stefano and Ruggeri, Massimiliano and Zagurskis, Valerijs}
}
@conference {17737,
	title = {System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach},
	booktitle = {Proceedings of the 15th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD{\textquoteright}12)},
	year = {2012},
	month = {September 5-8},
	address = {Izmir, Turkey},
	abstract = {Modern embedded systems increasingly require adaptive run-time management. The system may adapt the mapping of the applications in order to accommodate the current workload conditions, to balance load for efficient resource utilization, to meet quality of service agreements, to avoid thermal hot-spots and to reduce power consumption. As the possibility of experiencing run-time faults becomes increasingly relevant with deep-sub-micron technology nodes, in the scope of the MADNESS project, we focus particularly on the problem of graceful degradation by dynamic remapping in presence of run-time faults. In this paper, we summarize the major results achieved in the MADNESS project until now regarding the system adaptivity and fault tolerant processing. We report the first results of the integration between platform level and middleware level support for adaptivity and fault tolerance. A case study demonstrates the survival ability of the platform via a low-overhead process migration mechanism and a near-optimal online remapping heuristic.},
	keywords = {fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), process migration, system adaptivity},
	doi = {http://dx.doi.org/10.1109/DSD.2012.122},
	author = {Meloni, Paolo and Tuveri, Giuseppe and Raffo, Luigi and Cannella, Emanuele and Stefanov, Todor and Derin, Onur and Fiorin, Leandro and Sami, Mariagiovanna}
}
@conference {17766,
	title = {System Level Approach to Denial-of-Service Detection in MPSoCs},
	booktitle = {Proceedings of the 7th Workshop on Embedded Systems Security (WESS{\textquoteright}2012), A Workshop of the Embedded Systems Week (ESWEEK{\textquoteright}12)},
	year = {2012},
	month = {10/2012},
	abstract = {Multiprocessor Systems-on-Chip (MPSoCs) are pervading our lives, acquiring ever increasing relevance in a large number of applications, including even safety-critical ones. MPSoCs, are becoming increasingly complex and heterogeneous; the increased complexity as well as the networking approach in turn make security aspects more critical. In this work we propose and implement a hierarchical multi-agent approach providing solutions to secure Network-on-Chip based MPSoCs at different levels of design from nondeterministic attacks such as Denial-of-Service (DoS). We develop a flexible, scalable and modular structure integrating protection of different elements in the MPSoC (e.g. memory, processors) that can be tuned to particular attack scenarios - in this case a DoS attack. This work aims at providing a comprehensive, system-level protection strategy: this constitutes its main methodological contribution. We prove feasibility of the concepts via prototype realization in FPGA technology.},
	author = {Lukovi{\'c}, Slobodan and Srivastava, Anubhav}
}
@conference {147.TaMoFe11,
	title = {System Policies for Gradual Tuning of Security and Workload in Wireless Sensor Networks},
	booktitle = {Proceedings of the IEEE Wireless Telecommunication Symposium (WTS)},
	year = {2011},
	month = {April},
	address = {New York, USA},
	abstract = {In wireless sensor networks (WSN) energy consumption is a key issue. Security of communications, with its demand of computational resources, as well as performances are other fundamental issues. Finding a trade-off between performance and energy consumption, yet providing an adequate level of security is very challenging. Traditional solutions for the aforementioned problem assume that the operative environment is well-known and static, thus limiting the flexibility of the system. In this paper, instead, we propose a self-adaptation mechanism for gradual adaption of security and system workload in WSNs. The adaptation process can be tuned by using specific policies both for controlling the running tasks and for customizing the behavior of the self-adaptation mechanism. The ultimate goal is to perform adaptations by maximizing system performances while satisfying power constraints. A case study, implemented on Sun SPOTs, is also presented to show how the self-adaptation mechanism works in a real sensor node.},
	doi = {http://dx.doi.org/10.1109/WTS.2011.5960883},
	author = {Taddeo, Antonio Vincenzo and Morales, Luis Germ{\'a}n Garcia and Ferrante, Alberto}
}
@conference {121.DeFe10,
	title = {Scheduling energy consumption with local renewable micro-generation and dynamic electricity prices},
	booktitle = {CPSWEEK/GREEMBED 2010: Proceedings of the First Workshop on Green and Smart Embedded System Technology: Infrastructures, Methods and Tools},
	year = {2010},
	month = {April},
	address = {Stockholm, Sweden},
	abstract = {The electricity market is going through a deep modification as it is moving toward the integration of smart grids. Future homes will include smarter electric devices that will be easily managed from the power consumption stand point. The capability of performing short-term negotiation of energy purchases, if introduced and if efficiently exploited, will give the user the ability to reduce energy costs. In this paper we discuss a scheduling problem for household tasks that will help users save money spent on their energy consumption. Our system model relies on electricity price signals, availability of locally-generated power and flexible tasks with deadlines. A case study shows that cost savings are possible but fast and efficient solutions to the scheduling problem are needed for their real world use.},
	keywords = {scheduling, smart grid, smart home},
	author = {Derin, Onur and Ferrante, Alberto}
}
@conference {17743,
	title = {Security and Packets Delivery Trade-Off for WSN},
	booktitle = {Consumer Communications and Networking Conference (CCNC), 2010 7th IEEE},
	year = {2010},
	abstract = {The optimization of resources to be used for securing transmissions in wireless sensor networks while retaining communication quality of service is a challenging task. In this paper, we propose an energy-aware mechanism to determine the most efficient set of packets to be processed according with the resource consumed and the packets delivery requirements.},
	keywords = {authentication, costs, data security, delay, energy consumption, energy-aware mechanism, information security, network security, packet radio networks, packets delivery requirements, packets delivery trade-off, protection, quality of service (QoS), runtime, telecommunication security, wireless sensor networks, WSN},
	doi = {10.1109/CCNC.2010.5421689},
	author = {Taddeo, Antonio Vincenzo and Ferrante, Alberto}
}
@conference {137.VuLuErKu10.3,
	title = {A Smart Metering Architecture as a step towards Smart Grid realization},
	booktitle = {Proceedings of the IEEE EnergyCon 2010},
	year = {2010},
	month = {December 18-22},
	address = {Bahrain},
	abstract = {Emerging concept of Smart Grids aims at increasing visibility and controllability of electricity grids boosting their operational efficiency, enabling novel enhanced services to customers and utilities at a same time. Successful realization of this concept will in great part depend on efficient management of tremendous amounts of data to be gathered and processed in very short time periods. In this work we propose a novel smart metering architecture to manage data collected from deployed smart meters logically encapsulated in form of virtual meters. The metering infrastructure is structured in the form of Advanced Metering Infrastructure (AMI). The architecture of Meter Data Management (MDM) system as well and its integration in Control Center structure of power system is described in details. The testing and verification of proposed solution is performed on data from power distribution company Vattenfall, Sweden.},
	doi = {http://dx.doi.org/10.1109/ENERGYCON.2010.5771705},
	author = {Vukmirovi{\'c}, Srdjan and Lukovi{\'c}, Slobodan and Erdeljan, Aleksandar and Kuli{\'c}, Filip}
}
@conference {122.VuErKuLu10,
	title = {Software architecture for Smart Metering systems with Virtual Power Plant},
	booktitle = {Proceedings of the 15th IEEE Mediterranean Electrotechnical Conference (MELECON2010)},
	year = {2010},
	month = {April},
	address = {La Valleta, Malta},
	abstract = {This paper presents a novel architecture for Smart Metering systems which enables their seamless, secure and efficient integration in wider SmartGrid software structures. Smart metering solutions represent one of the fastest evolving areas in the field of power distribution systems. There is an extensive interest of leading software vendors in the field, for development of architectures that can efficiently manage transmission, processing and storing of tremendous amount of data produced by such metering devices deployed at the end-end side. The integration of these systems into existing power system software architectures (outage management, workforce management, etc.) represents a major challenge for research community. In such an environment it is extremely important to adopt standardized data exchange mechanisms. The proposed architecture is conceived as modular and scalable structure so that it can help implementation of novel power distribution concepts such as Virtual Power Plants (VPPs). The proposed architecture has been successfully tested and verified in real-life operation as one of modules of Smart Metering system named Meter Data Management (MDM) developed by Telvent DMS Llc, Serbia.},
	doi = {http://dx.doi.org/10.1109/MELCON.2010.5476237},
	author = {Vukmirovi{\'c}, Srdjan and Erdeljan, Aleksandar and Kuli{\'c}, Filip and Lukovi{\'c}, Slobodan}
}
@conference {131.VuLuErKu10,
	title = {A solution for CIM based integraton of Meter Data Management in Control Center of a power system},
	booktitle = {Proceedings of the 2010 IEEE Workshop on Environmental, Energy, and Structural Monitoring Systems (EESMS{\textquoteright}10)},
	year = {2010},
	month = {September 9},
	address = {Taranto, Italy},
	abstract = {Modern power systems, in particular Control Center structures, involve more and more software applications in their normal operation. Such scenario urges for standardization of inter and intra processes communication and data exchange. In this work we propose a solution for seamless Meter Data Management (MDM) integration with Control Center structures through Common Information Model (CIM). The solution is implemented in form of a wrapper that adopts messages (i.e. payloads) to the standard requested form. The proposed solution has been verified using a simulation framework which emulates regular control and data.},
	keywords = {monitoring and control, system level modeling, virtual power plants},
	doi = {http://dx.doi.org/10.1109/EESMS.2010.5634169},
	author = {Vukmirovi{\'c}, Srdjan and Lukovi{\'c}, Slobodan and Erdeljan, Aleksandar and Kuli{\'c}, Filip}
}
@conference {123.LuPeFi10,
	title = {Stack Protection Unit as a step towards securing MPSoCs},
	booktitle = {Proceedings of 24th IEEE International Parallel and Distributed Processing Symposium (IPDPS)},
	year = {2010},
	month = {April 19-23},
	address = {Atlanta, USA},
	abstract = {Reconfigurable technologies are getting popular as an instrument for not only verification and prototyping but also commercial implementation of Multi-Processor Systems-on-Chip (MPSoC) architectures. At the same time, these systems in particular Networks-on-Chip (NoCs) based ones, have emerged as a design strategy to cope with increased requirements and complexity of modern applications. Nevertheless, increasing heterogeneity coupled with possibility of reconfiguration makes security become one of major concerns in MPSoC design. Protection strategies must consider attack scenarios at both levels - individual cores and system level security. This work represents an element in a wider security framework, it shows a solution against one of the most widespread types of attacks - code injection. Our response to tackle this challenge is given in form of Stack Protection Unit (SPU) embedded into processing core. MicroBlaze soft-core processor serves as a case study for verification of the proposed solution in FPGA technology.},
	keywords = {FPGA, microblaze, security, stack protection unit},
	doi = {http://dx.doi.org/10.1109/IPDPSW.2010.5470728},
	author = {Lukovi{\'c}, Slobodan and Pezzino, Paolo and Fiorin, Leandro}
}
@conference {113.LuCoKu10,
	title = {A system level model of possible integration of Building Management System in SmartGrid},
	booktitle = {Complexity in Engineering (COMPENG 2010)},
	year = {2010},
	month = {February 22-24},
	address = {Rome, Italy},
	abstract = {SmartGrids are conceived as modular, end-to-end interoperable systems. It is envisaged that power systems components (modules) will be hierarchically coordinated and integrated in order to form certain autonomous clusters which would perform as much as possible local data storing and processing in order to decrease overall communicational and computational overhead. Building Management Systems (BMS) could be seen as one of such modules inside wider SmartGrid system. The incorporation of BMS must consider both technical as well as commercial issues. Hence, the efficient integration will require standards{\textquoteright} harmonization and closer interaction among key elements of these systems. Moreover, another important issue will be adopting of new market models to BMS. In order to represent the system and relations among its components in a clear and understandable fashion, we introduce system level modeling concept as an instrument to bridge functional requirements and implementation constraints.},
	doi = {http://dx.doi.org/10.1109/COMPENG.2010.43},
	author = {Lukovi{\'c}, Slobodan and {\v C}ongradac, Velimir and Kuli{\'c}, Filip}
}
@inbook {92.FiPaSi09.2,
	title = {Security in NoC},
	booktitle = {Networks-on-Chips: Theory and Practice},
	year = {2009},
	pages = {157-194},
	publisher = {Taylor and Francis Group, LLC - CRC Press},
	organization = {Taylor and Francis Group, LLC - CRC Press},
	abstract = {Future integrated systems will contain billion of transistors, composing tens to hundreds of IP cores. These IP cores, implementing emerging complex multimedia and network ap- plications, should be able to deliver rich multimedia and networking services. An efficient cooperation among these IP cores (e.g., efficient data transfers) can be achieved through utilization of the available resources. The design of such complex systems includes several challenges to be addressed. Among others one challenge is to design an on-chip interconnection network that should be able to efficiently connect the IP cores. Another challenge is to derive such an application mapping that will make efficient usage of the available hardware resources . An architecture that is able to accommodate such a high number of cores, satisfying the need for commu- nication and data transfers, is the Network-on-Chip (NoC) architecture. For these reasons Networks-on-Chip become a popular choice for designing the on-chip interconnect for Systems-on-Chip (MPSoCs), and are supported from the industry (such as the Ethereal NoC from Philips, the STNoC from STMicroelectronics and an 80-core NoC from Intel). As it is presented in , the key design challenges of emerging NoC design are a) the communication infrastructure, b) the communication paradigm selection and c) the application mapping optimization.},
	keywords = {network-on-chip (NoC), security},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina and Elmiligi, Haytham},
	editor = {Gebali, Fayez and El-Kharashi, Watheq}
}
@conference {17769,
	title = {A Security Service Protocol for MANETs},
	booktitle = {Consumer Communications and Networking Conference. CCNC 2009},
	year = {2009},
	month = {01/2009},
	publisher = {IEEE},
	organization = {IEEE},
	address = {in Las Vegas, Nevada, USA},
	abstract = {Mobile ad-hoc networks are composed of heterogeneous mobile systems. Securing their communications may be difficult due to differences in the supported algorithms and protocols. In this paper we propose a protocol to negotiate security settings for the communications. This protocol aims at minimizing the power consumption and at providing the highest possible security level associated with the communications.},
	keywords = {ad hoc networks, communication system security, data security, decision support systems, energy consumption, hardware, heterogeneous mobile systems, MANET, mobile ad-hoc networks, mobile communication, mobile radio, power consumption, power system security, protocol, quality of service (QoS), routing protocols, security service protocol, telecommunication security},
	doi = {10.1109/CCNC.2009.4784782},
	author = {Taddeo, Antonio Vincenzo and Ferrante, Alberto}
}
@conference {103.MuMuPr09,
	title = {Semi-Automated HW/SW Co-design for Embedded Systems: from MARTE Models to SystemC Simulators},
	booktitle = {FDL{\textquoteright}09 Proceedings},
	year = {2009},
	month = {September 22-24},
	address = {Sophia-Antipolis, France},
	abstract = {Although MDE and Hw/Sw Co-design are widely used to address the design complexity problem, the lack of design procedures and methodologies joining both concepts restrains their usage as complementary techniques, thus preventing the implementation of faster and more robust design cycles. In this paper we present a practical semi-automated design flow where both methodologies are merged and exploited to enable a fast design process targeting highly complex Real-Time Embedded Systems, executing several tasks on SoC and MPSoC devices, while allowing the usage of Design Space Exploration, Schedulability Analysis and Estimation techniques.},
	author = {Murillo, Luis Gabriel and Mura, Marcello and Prevostini, Mauro}
}
@conference {100.DeFe09,
	title = {Simulation of a Self-adaptive Run-time Environment with Hardware and Software Components},
	booktitle = {SINTER {\textquoteright}09: Proceedings of the 2009 ESEC/FSE workshop on Software integration and evolution @ runtime},
	year = {2009},
	month = {August},
	pages = {37{\textendash}40},
	publisher = {ACM},
	organization = {ACM},
	address = {Amsterdam, The Netherlands},
	abstract = {In this paper we describe a new way for simulating self-adaptive systems developed by relying on a component-based approach, this approach proves to be useful both in easing self-adaptivity and in providing the ability to mix hardware and software elements. Our simulation method is based on SACRE (Self-Adaptive Component Run-time Environment), a framework we have defined in Java for simulating self-adaptive systems.},
	keywords = {component-based design, HW/SW co-design, self-adaptive systems, simulation},
	isbn = {978-1-60558-681-6},
	doi = {http://doi.acm.org/10.1145/1596495.1596507},
	author = {Derin, Onur and Ferrante, Alberto}
}
@article {84.AlGaSte2008,
	title = {Secure Memory Accesses on Networks-on-Chip},
	journal = {IEEE Transactions on Computers},
	volume = {57},
	number = {9},
	year = {2008},
	month = {September},
	pages = {1216-1229},
	abstract = {Security is gaining relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses security aspects related to Network on Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based multiprocessor systems, we focus on the topic, not yet thoroughly faced, of data protection. In this paper, we present a secure NoC architecture composed of a set of Data Protection Units (DPUs) implemented within the Network Interfaces (NIs)1. The run-time configuration of the programmable part of the DPUs is managed by a central unit, the Network Security Manager (NSM). The DPU, similar to a firewall, can check and limit the access rights (none, read, write, or both) of processors accessing data and instructions in a shared memory. In particular, the DPU can distinguish between the operating roles (supervisor/user and secure/non secure) of the processing elements.We explore alternative implementations of the DPU and demonstrate how this unit does not affect the network latency if the memory request has the appropriate rights. We also focus on the dynamic updating of the DPUs to support their utilization in dynamic environments, and on the utilization of authentication techniques to increase the level of security.},
	keywords = {data protection, embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1109/TC.2008.69},
	author = {Fiorin, Leandro and Palermo, Gianluca and Lukovi{\'c}, Slobodan and Catalano, Valerio and Silvano, Cristina}
}
@conference {88.FiPaSi08,
	title = {A Security Monitoring Service for NoCs},
	booktitle = {Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS{\textquoteright}08)},
	year = {2008},
	month = {10/2008},
	address = {Atlanta, Georgia, USA.},
	abstract = {As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. Networks-on- Chip (NoCs) have appeared as design strategy to cope with the rapid increase in complexity of Multiprocessor Systems- on-Chip (MPSoCs), but only recently research community have addressed security on NoC-based architectures. In this paper, we present a monitoring system for NoC based architectures, whose goal is to help detect security violations carried out against the system.Information col- lected are sent to a central unit for efficiently counteracting actions performed by attackers.We detail the design of the basic blocks and analyse overhead associated with the ASIC implementation of the monitoring system, discussing type of security threats that it can help detect and counteract.},
	keywords = {embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1145/1450135.1450180},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina}
}
@conference {64.Barcellona2,
	title = {SC2: State Charts to System C: Automatic Executable Models Generation},
	booktitle = {proceedings FDL07},
	year = {2007},
	month = {September},
	address = {Barcelona, Spain},
	abstract = {The recent development of embedded systems calls for the necessity of a complete framework for design and simulation of applications that span through all levels of system design. Desirable characteristics of such a framework are rapidity of use, simplicity and reusability. For this purpose we already introduced a generator that converts specifications written with a subset of StateCharts to behavioral SystemC [9] [11]. In this paper we present the new version of our tool: most of the limitations of the previous versions have been overcome, the considered subset of the StateCharts formalism has been extended and the target has been changed from behavioral to Register Tranfer Level (RTL) SystemC. A major enhancement of this new version is the possibility of obtaining various module instances starting from a single specification, which is vital in some contexts (e.g. Wireless Sensors Networks simulation). The semantics chosen for our StateCharts diagrams is clearly described. The generation of executable models as well as the kernel template of the generated code are discussed in detail.},
	keywords = {code generation, StateCharts, SystemC, unified modeling language (UML)},
	author = {Mura, Marcello and Paolieri, Marco}
}
@article {51.TaFe07,
	title = {Scheduling Small packets in IPSec Multi-accelerator Based Systems},
	journal = {Journal of Communication(JCM) Academy publisher},
	volume = {2},
	number = {2},
	year = {2007},
	month = {March},
	pages = {53-60},
	address = {Stresa, Italy},
	abstract = {IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. IPSec accelerator performance may heavily depend on the dimension of the packets to be processed. In fact, when packets are small, the time needed to transfer data and to set up the accelerators may exceed the one to process (e.g. to encrypt) the packets by software. In this paper we present a packet scheduling algorithm that tackles this problem. Packets belonging to the same Security Association are grouped before the transfer to the accelerators. Thus, the transfer and the initialization time have a lower influence on the total processing time of the packets. This algorithm also provides the capability of scheduling grouped packets over multiple cryptographic accelerators. High-level simulations of the scheduling algorithm have been performed and the results for a one-accelerator and for a two-accelerator system are also shown in this paper.},
	keywords = {accelerator, HW/SW co-design, IPSec, scheduling algorithm, security},
	author = {Taddeo, Antonio Vincenzo and Ferrante, Alberto}
}
@conference {60.FiSiSa07,
	title = {Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations},
	booktitle = {DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07)},
	year = {2007},
	month = {August 29-31},
	address = {L{\"u}beck, Germany},
	abstract = {Security has gained increasing relevance in the development of embedded devices. Towards the aim of a secure system at each level of the design, in this paper we address security aspects related to Networks-on-Chips (NoCs) architectures. After presenting the attacks most likely to address NoCs, we survey existing academic and industrial secure architectures relevant to our case, focusing in particular on their communication infrastructure. We outline and propose possible solutions to contrast some of the attacks described and suggest the use of the NoC as a mean to monitor and detect unexpected system behaviors.},
	keywords = {embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1109/DSD.2007.4341520},
	author = {Fiorin, Leandro and Silvano, Cristina and Sami, Mariagiovanna}
}
@conference {56.FeTaSaMa07,
	title = {Self-adaptive Security at Application Level: a Proposal},
	booktitle = {ReCoSoC 2007, Jun. 2007, in proceedings of ReCoSoC 2007},
	year = {2007},
	month = {June},
	abstract = {Self-adaptive systems have the ability to adapt themselves to mutating external or internal conditions without requesting any intervention of the user; the security of such systems is influenced by those adaptations. Therefore, also the security mechanisms that are put in place by the operating system, should adapt to maintain the desired security level. This paper proposes a self-adaptive framework for the system security. This adaptation scheme allows the system to choose the best set of security policies at every given time; this set is determined by considering the system internal and external conditions as well as the application requirements. The proposed framework deals with self-adaptation at system level in order to provide both a domain independent and a flexible solution.},
	keywords = {autonomous systems, security, security policies, self-adaptive security, self-adaptive systems, system level design},
	author = {Ferrante, Alberto and Taddeo, Antonio Vincenzo and Sami, Mariagiovanna and Mantovani, Fabrizio and Fridkins, Jurijs}
}
@conference {59.ReBaEi07,
	title = {Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies},
	booktitle = {International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07)},
	year = {2007},
	month = {July 16-19},
	address = {Samos, Greece},
	abstract = {This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from DPA and similar side-channel attacks. In order to demonstrate the effectiveness of different logic styles against power analysis attacks, the non-linear bijective function of the Kasumi algorithm (known as substitution box S7) was implemented with CMOS and MCML technology, and a set of attacks was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, only very few attacks to MCML were successful.},
	keywords = {current mode logic (CML), differential power analysis (DPA), power simulation, side channel attacks},
	author = {Regazzoni, Francesco and Badel, St{\'e}phane and Eisenbarth, Thomas and Gro{\ss}sch{\"a}dl, Johann and Poschmann, Axel and Toprak, Zeynep and Macchetti, Marco and Pozzi, Laura and Paar, Christof and Leblebici, Yusuf and Ienne, Paolo}
}
@conference {50.MuPaNeSa07,
	title = {StateCharts to SystemC: a High Level Hardware Simulation Approach},
	booktitle = {Proceedings of GLSVLSI 2007},
	year = {2007},
	month = {March 11-13},
	address = {Stresa, Italy},
	abstract = {In this paper we present a tool that converts specifications written with a subset of StateCharts into SystemC behavioral models. The main advantages of such an approachare rapidity of use, simplicity and reusability. Various systems can be modeled at different levels of abstraction and accuracy through StateCharts and different peculiar aspects (e.g. energy, performances) can be taken into consideration. Moreover different parts of the design can be identified at different detail levels. The kernel of the simulator is fully discussed together with its mapping to the semantics of our StateCharts diagrams. As a case study we present here a model of the IBM PowerPC 750 Cache system and the respective SystemC simulator automatically generated by our tool.},
	keywords = {code generation, StateCharts, SystemC, unified modeling language (UML)},
	doi = {http://dx.doi.org/10.1145/1228784.1228904},
	author = {Mura, Marcello and Paolieri, Marco and Negri, Luca and Sami, Mariagiovanna}
}
@conference {41.TaFePi2006,
	title = {Scheduling Small Packets in IPSec-based Systems},
	booktitle = {CCNC},
	year = {2006},
	month = {January 8},
	address = {Las Vegas, NV, USA},
	abstract = {IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. IPSec accelerator performance may heavily depend on the dimension of the packets to be processed. When packets are small, the time needed to transfer data and to set up the accelerator may exceed the one to process the packets (e.g. to encrypt) by software. In this paper, we propose a solution for this problem. High-level simulations and the related results are provided to show the properties of the algorithm.},
	keywords = {accelerator, HW/SW co-design, IPSec, scheduling algorithm, security},
	doi = {http://dx.doi.org/10.1109/CCNC.2006.1593123},
	author = {Taddeo, Antonio Vincenzo and Ferrante, Alberto and Piuri, Vincenzo}
}
@conference {39.1169233,
	title = {Speeding Up AES By Extending a 32 bit Processor Instruction Set},
	booktitle = {ASAP {\textquoteright}06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP{\textquoteright}06)},
	year = {2006},
	pages = {275-282},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {Nowadays the need of speed in cipher and decipher operations is more important than in the past. This is due to the diffusion of real time applications, which fact involves the use of cryptography. Many co-processors for cryptography were studied and presented in the past, but only few works were addressed to the enhancement of the instruction set architecture (ISA) of the embedded processor. This paper presents an extension of the ISA of a 32 bit processor, that aims at speeding up the software implementations of the AES algorithm. After the identification of the most frequently executed and the most time consuming sections of the algorithm, a set of dedicated instructions is designed in order to improve the performances of the cipher operations. We validate our instruction set extension by measuring the speed up for different optimized implementations of AES using an ARM processor simulator, but the enhancements we propose are general enough to be applied to almost all 32 bit processors.},
	keywords = {cryptography, HW/SW co-design, instruction set extension},
	isbn = {0-7695-2682-9},
	doi = {http://dx.doi.org/10.1109/ASAP.2006.62},
	author = {Bertoni, Guido Marco and Breveglieri, Luca and Farina, Roberto and Regazzoni, Francesco}
}
@conference {35.MacRiv2005,
	title = {Small-scale Variants of the Secure Hash Standard},
	booktitle = {ECRYPT workshop on RFID and lightweight cryptography},
	year = {2005},
	month = {July 14-15},
	address = {Graz, Austria},
	abstract = {In this paper we present effective small scale formulations of the Secure Hash Standard; we focus on the SHA-2 family of algo- rithms, introducing new compact instances baptized SHA-16, SHA-32, and SHA-64. These may be useful for computing hashes and Message Authentication Codes (MACs) on small platforms where only 8-bit pro- cessors are available, such as in the case of Radio Frequency Identifi- cation (RFID) devices and embedded systems. To prove the soundness of our scaling approach, we analyze the cryptographic properties of the proposed constructions in terms of adherence to the Strict Avalanche Criterion (SAC) and of robustness to birthday attacks, by also compar- ing the results with the expected values from random functions. As an additional contribution, we complete the theoretical results for the bal- ance property of random functions, thereby also calculating the expected robustness of the original SHA-2 family versus birthday attacks. Keywords: hash functions, balance, SAC, small scale, RFID.},
	keywords = {balance, hash functions, RFID, SAC, small scale},
	author = {Macchetti, Marco and Rivard, Philippe}
}
@conference {29.SaMaRe2005,
	title = {Speeding Security on the Intel StrongARM},
	booktitle = {Embedded Intel Solutions},
	year = {2005},
	pages = {31-33},
	abstract = {With the increasing use of portable and wireless devices in the business and daily life, protecting sensitive information via encryption is becoming more and more crucial. ALaRI (Advanced Learning and Research Institute) has been conducting research aimed at improving the execution of security algorithms in embedded systems. Thanks to a donation from Intel, ALaRI has been able to develop several recommendations for implementing security efficiently on the Intel StrongARM architecture.},
	keywords = {embedded processors, instruction set extension, security},
	author = {Sami, Mariagiovanna and Macchetti, Marco and Regazzoni, Francesco}
}
@conference {7.MiMaMaPre,
	title = {System-level design of embedded applications by UML: the Wireless Meter Reading case},
	booktitle = {MSy2002 Workshop},
	year = {2002},
	month = {October 3-4},
	pages = {181-187},
	address = {Winterthur},
	abstract = {The Unified Modeling Language (UML) is a language for specifying, visualizing, constructing, and documenting the artifacts of software systems, as well as for business modeling and other non-software systems. The UML represents a collection of best engineering practices that have proven successful in the modeling of large and complex systems; it is interesting to envision its extension for specification and modeling of hardwaresoftware systems as well, since the first design phases, i.e. before hardware-software partitioning has been effected. This paper describes how UML has been used in the design of a wireless meter reading system consisting of hardware and software components.},
	keywords = {embedded applications, unified modeling language (UML), wireless meter reading},
	author = {Minosi, Antonio and Martinola, Aris and Mankan, Srinivas and Prevostini, Mauro}
}
@conference {2.BoSaMa2001,
	title = {The {\textquoteright}Smart Card System{\textquoteright} project: From plastic money to mobile transaction support},
	booktitle = {Technology Leadership Day - organized by the MicroSwiss Network},
	year = {2001},
	month = {October 10},
	address = {Fribourg},
	author = {Bondi, Umberto and Saraceno, Giuseppe and Mazzoni, Luca}
}
