@inbook {18571,
	title = {Fault Attacks, Injection Techniques and Tools for Simulation},
	booktitle = {Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment},
	year = {2017},
	pages = {149-167},
	publisher = {Springer},
	organization = {Springer},
	edition = {First edition; 2016},
	author = {Piscitelli, Roberta and Bhasin, Shivam and Regazzoni, Francesco}
}
@conference {18480,
	title = {Fault attacks, injection techniques and tools for simulation},
	booktitle = {10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015},
	year = {2015},
	month = {04/2015},
	pages = {1-6},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Naples, Italy},
	abstract = {Faults attacks are a serious threat to secure devices, because they are powerful and they can be performed with extremely cheap equipment. Resistance against fault attacks is often evaluated directly on the manufactured devices, as commercial tools supporting fault evaluation do not usually provide the level of details needed to assert the security of a device. Early identification of weak points would instead be very useful as it would allow to immediately apply the appropriate countermeasures directly at design time. Moving towards this goal, in this work, we survey existing fault attacks and techniques for injecting faults, and we analyze the suitability of existing electronic design automaton commodities for estimating resistance against fault attacks. Our exploration, which includes the type of attacks that can be simulated and the limitations of each considered simulation approach, is an initial step towards the development of a complete framework for asserting fault attack robustness},
	keywords = {fault attacks robustness, fault resilience, injection techniques, secure devices, security, security of data},
	isbn = {978-1-4799-1999-4},
	doi = {10.1109/DTIS.2015.7127352},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7118811},
	author = {Piscitelli, Roberta and Bhasin, Shivam and Regazzoni, Francesco}
}
@article {18061,
	title = {A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints},
	journal = {IEEE Transactions on Circuits and Systems II},
	volume = {59},
	issue = {12},
	year = {2013},
	pages = {947-951},
	abstract = {Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (Vdd) and threshold (Vt) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the Vdd/Vt MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all Vdd/Vt pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC{\textquoteright}99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10\% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4{\texttimes} compared to a conventional flow with Vdd scaling only.},
	issn = {1549-7747},
	doi = {10.1109/TCSII.2012.2231034},
	author = {Bol, David and Hocquet, C{\'e}dric and Regazzoni, Francesco}
}
@article {18491,
	title = {A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints},
	journal = {IEEE Transactions on Circuits and Systems II: Express Briefs  },
	volume = {59-II},
	issue = {12},
	year = {2012},
	month = {02/2012},
	pages = {947-951},
	type = {journal},
	chapter = {947},
	abstract = {Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (Vdd) and threshold (Vt) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the Vdd/Vt MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all Vdd/Vt pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC{\textquoteright}99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10\% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4{\texttimes} compared to a conventional flow with Vdd scaling only},
	keywords = {circuit optimisation, CMOS logic circuits, fast ULV logic synthesis flow, Low power electronics},
	issn = {1549-7747},
	doi = {10.1109/TCSII.2012.2231034},
	url = {http://dx.doi.org/10.1109/TCSII.2012.2231034},
	author = {Bol, David and Hocquet, C{\'e}dric and Regazzoni, Francesco}
}
@conference {18080,
	title = {A First Step Towards Automatic Application of Power Analysis Countermeasures},
	booktitle = {48th Design Automation Conference (DAC)},
	year = {2011},
	month = {June},
	address = {San Diego, Califorina},
	author = {Bayrak, Ali Galip and Regazzoni, Francesco and Brisk, Philip and Standaert, Fran{\c c}ois-Xavier and Ienne, Paolo}
}
@conference {18086,
	title = {FPGA Implementations of the AES Masked Against Power Analysis Attacks},
	booktitle = {2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE)},
	year = {2011},
	month = {February},
	address = {Darmstadt, Germany},
	author = {Regazzoni, Francesco and Yi, Wang and Standaert, Fran{\c c}ois-Xavier}
}
@conference {18077,
	title = {Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks},
	booktitle = {10th Smart Card Research and Advanced Application Conference (CARDIS)},
	year = {2011},
	month = {September},
	address = {Leuven, Belgium},
	author = {Medwed, Marcel and Petit, Christophe and Regazzoni, Francesco and Renauld, Mathieu and Standaert, Fran{\c c}ois-Xavier}
}
@conference {18083,
	title = {Fresh Re-Keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices},
	booktitle = {Proceedings of Progress in Cryptology - Africacrypt},
	year = {2010},
	month = {May},
	address = {Stellenbosch, South Africa},
	author = {Medwed, Marcel and Standaert, Fran{\c c}ois-Xavier and Gro{\ss}sch{\"a}dl, Johann and Regazzoni, Francesco}
}
