@article {18591,
	title = {Black-Hat High-Level Synthesis: Myth or Reality?},
	journal = {IEEE Transactions on Very Large Scale Integration Systems},
	year = {In Press},
	doi = {10.1109/TVLSI.2018.2884742},
	author = {Pilato, Christian and Basu, Kanad and Regazzoni, Francesco and Karri, Ramesh}
}
@conference {18556,
	title = {Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis},
	booktitle = {Advances in Parallel Computing},
	year = {2018},
	doi = {10.3233/978-1-61499-843-3-622},
	author = {Pilato, Christian}
}
@conference {152.KrLeAhPoLi11.SiPS,
	title = {Beamforming for interference mitigation and its implementation on an SDR baseband processor},
	booktitle = {SiPS{\textquoteright}11: Proceedings of the IEEE Workshop on Signal Processing Systems},
	year = {2011},
	month = {October 4-7},
	pages = {1{\textendash}6},
	address = {Beirut, Lebanon},
	abstract = {We present the first implementation of a distributed beamforming algorithm for interference mitigation on an SDR baseband processor. Co-channel interference (CCI) is becoming a major source of impairments in wireless communications and distributed beamforming is a promising technique to mitigate its negative impact. However, such schemes are challenging to implement in practical scenarios due to their complexity and synchronization requirements. In this paper, we report on implementation of a suboptimal, yet efficient, beamforming scheme for CCI mitigation and present the complexity modeling and algorithm transformations for achieving numerically stability. We also present the fixed-point quantization and the proper mapping on a parallel programmable baseband architecture aimed for software-defined radio (SDR). We optimize this algorithm for a coarse grained reconfigurable array (CGRA) processor and evaluate it in the context of the LTE standard.},
	keywords = {beamforming, coarse grained reconfigurable array (CGRA), fixed-point arithmetic, long term evolution (LTE), software defined radio (SDR)},
	doi = {http://dx.doi.org/10.1109/SiPS.2011.6088973},
	author = {Krdu, Adrian and Lebrun, Yann and Ahmad, Ubaid and Pollin, Sofie and Li, Min}
}
@article {18492,
	title = {Breaking ECC2K-130},
	journal = {IACR Cryptology ePrint Archive},
	volume = {2009},
	year = {2009},
	month = {11/2009},
	pages = {541},
	abstract = {Elliptic-curve cryptography is becoming the standard public-key primitive not only for mobile devices but also for high-security applications. Advantages are the higher cryptographic strength per bit in comparison with RSA and the higher speed in implementations. To improve understanding of the exact strength of the elliptic-curve discrete-logarithm problem, Certicom has published a series of challenges. This paper describes breaking the ECC2K-130 challenge using a parallelized version of Pollard{\textquoteright}s rho method. This is a major computation bringing together the contributions of several clusters of conventional computers, PlayStation~3 clusters, computers with powerful graphics cards and FPGAs. We also give /preseestimates for an ASIC design. In particular we present * our choice and analysis of the iteration function for the rho method; * our choice of finite field arithmetic and representation; * detailed descriptions of the implementations on a multitude of platforms: CPUs, Cells, GPUs, FPGAs, and ASICs; * details about running the attack. },
	keywords = {Attacks, automorphisms, binary fields, Certicom challenges, DLP, ECC, implementation, Koblitz curves, parallelized Pollard rho},
	url = {http://eprint.iacr.org/2009/541},
	author = {Bailey, Daniel V. and Batina, Lejla and Bernstein, Daniel J. and Birkner, Peter and Bos, Joppe W. and Chen, Hsieh - Chung and Cheng, Chen - Mou and van Damme, Gauthier and G{\"u}neysu, Tim and Gurkaynak, Frank and Kleinjung, Thorsten and Paar, Christof and Regazzoni, Francesco and Niederhagen, Ruben and Schwabe, Peter and Uhsadel, Leif and Van Herrewege, Anthony}
}
@conference {44.SivaPrev2006,
	title = {Bridging the Gap between SysML and Design Space Exploration},
	booktitle = {FDL{\textquoteright}06 Proceedings},
	year = {2006},
	month = {September 19-22},
	pages = {389-394},
	address = {Darmstadt, Germany},
	abstract = {In the last few years the embedded systems design discipline required new design methodologies and new specification languages to support system engineers in developing heterogeneous systems where hardware and software are combined. One of the emerging modeling languages for system designers is the UML-based language called Systems Modeling Language (SysML). One of the most important tasks to be addressed early in the system design phase is the Design Space Exploration (DSE). DSE helps designers in discovering the optimal solutions among all possible combinations after mapping functional to architectural specifications. This paper describes an approach on how to use SysML for a DSE analysis within a system design phase.},
	keywords = {design space exploration, HW/SW co-design, modeling languages, systems modeling language (SysML)},
	author = {Sivakumar, Ganesan and Prevostini, Mauro}
}
