@inbook {17695,
	title = {Dynamic Adaptation of Security and QoS in Energy-Harvesting Sensors Nodes},
	booktitle = {e-Business and Telecommunications},
	series = {Communications in Computer and Information Science},
	volume = {222},
	year = {2012},
	pages = {243-258},
	publisher = {Springer},
	organization = {Springer},
	address = { Berlin Heidelberg},
	keywords = {energy harvesting, priority, quality of service (QoS), security, wireless sensor networks},
	isbn = {978-3-642-25205-1},
	doi = {10.1007/978-3-642-25206-8_16},
	url = {http://dx.doi.org/10.1007/978-3-642-25206-8_16},
	author = {Taddeo, Antonio Vincenzo and Mura, Marcello and Ferrante, Alberto},
	editor = {Obaidat, Mohammad and Tsihrintzis, George and Filipe, Joaquim}
}
@conference {128.Taddeo2010c,
	title = {QoS and Security in Energy-harvesting Wireless Sensor Networks},
	booktitle = {Proceedings of ICETE SECRYPT},
	year = {2010},
	month = {July},
	address = {Athens, Greece},
	abstract = {Wireless sensor networks are composed of small nodes that might be used for a variety of purposes. Nodes communicate together through a wireless connection that might be subject to different attacks when the network is placed in hostile environments. Furthermore, the nodes are usually equipped with very small batteries providing limited battery life, therefore limited power consumption is of utmost importance for nodes. This is in clear opposition with the requirement of providing security to communications as security might be very expensive from the power consumption stand point. Energy harvesting methods can be used to recharge batteries, but, in most of the cases the recharge profile cannot be known in advance. Therefore, nodes might face periods of time in which no recharge is available and the battery level is low. In this paper we introduce an optimization mechanism that allows the system to change the communication security settings at runtime with the goal of improving node lifetime, yet providing a suitable security level. The optimization mechanism further improves energy consumption by putting in place a quality of service mechanism: when energy is scarce, the system tends to send only essential packets. As shown by the simulations presented in this paper, this mechanism optimizes the energy consumption among different recharges.},
	keywords = {energy harvesting, priority, quality of service (QoS), security, wireless sensor networks},
	author = {Taddeo, Antonio Vincenzo and Mura, Marcello and Ferrante, Alberto}
}
@conference {54.FePi07,
	title = {High-level Architecture of an IPSec-dedicated System on Chip},
	booktitle = {proceedings of NGI 2007},
	year = {2007},
	month = {May},
	publisher = {IEEE Press},
	organization = {IEEE Press},
	address = {Trondheim, Norway},
	abstract = {IPSec is a suite of protocols which adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. In this paper we propose a high level architecture of a System on Chip (SoC) which implements IPSec. This SoC has been thought to be placed on the main data path of the host machine (flow-through architecture), thus allowing for transparent processing of IPSec traffic. The functionalities of the different blocks and their interactions, along with an estimation of the internal memory size, are also shown.},
	keywords = {accelerator, IPSec, priority, quality of service (QoS), security, system-on-chip (SoC), SystemC},
	author = {Ferrante, Alberto and Piuri, Vincenzo}
}
@conference {55.DaFeMa,
	title = {A Memory Unit for Priority Management in IPSec Accelerators},
	booktitle = {proceedings of ICC07. Glasgow, Scotland: IEEE Communications Society},
	year = {2007},
	month = {June 24},
	address = {Glasgow, Scotland},
	abstract = {This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support Quality of Service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed.},
	keywords = {accelerator, IPSec, priority, quality of service (QoS), security, system-on-chip (SoC), SystemC},
	doi = {http://dx.doi.org/10.1109/ICC.2007.257},
	author = {Dadda, Luigi and Ferrante, Alberto and Macchetti, Marco}
}
