@conference {18480,
	title = {Fault attacks, injection techniques and tools for simulation},
	booktitle = {10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015},
	year = {2015},
	month = {04/2015},
	pages = {1-6},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Naples, Italy},
	abstract = {Faults attacks are a serious threat to secure devices, because they are powerful and they can be performed with extremely cheap equipment. Resistance against fault attacks is often evaluated directly on the manufactured devices, as commercial tools supporting fault evaluation do not usually provide the level of details needed to assert the security of a device. Early identification of weak points would instead be very useful as it would allow to immediately apply the appropriate countermeasures directly at design time. Moving towards this goal, in this work, we survey existing fault attacks and techniques for injecting faults, and we analyze the suitability of existing electronic design automaton commodities for estimating resistance against fault attacks. Our exploration, which includes the type of attacks that can be simulated and the limitations of each considered simulation approach, is an initial step towards the development of a complete framework for asserting fault attack robustness},
	keywords = {fault attacks robustness, fault resilience, injection techniques, secure devices, security, security of data},
	isbn = {978-1-4799-1999-4},
	doi = {10.1109/DTIS.2015.7127352},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7118811},
	author = {Piscitelli, Roberta and Bhasin, Shivam and Regazzoni, Francesco}
}
@conference {18462,
	title = {Security Challenges for Hardware Designers of Mobile Systems},
	booktitle = {2015 Mobile Systems Technologies Workshop (MST)},
	year = {2015},
	month = {May},
	keywords = {cryptographic capabilities, cryptographic primitives, cryptography, hardware, hardware design flow, hardware designers, hardware trojan, Hardware Trojans, Integrated optics, malware, mobile communication, mobile computing, mobile device, mobile devices, Mobile handsets, mobile systems, Optical device fabrication, pervasive mobile devices, physical attack, physical attacks, security, security challenges, software malware, telecommunication security, Trojan horses},
	doi = {10.1109/MST.2015.11},
	author = {Milosevic, Jelena and Ferrante, Alberto and Regazzoni, Francesco}
}
@conference {18468,
	title = {(THOR) - The hardware onion router},
	booktitle = {24th International Conference on Field Programmable Logic and Applications, (FPL) 2014},
	year = {2014},
	month = {09/2014},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Munich, Germany},
	abstract = {Security and privacy of data traversing internet have always been a major concern for all users. In this context, The Onion Routing (Tor) is the most successful protocol to anonymize global Internet traffic and is widely deployed as software on many personal computers or servers. In this paper, we explore the potential of modern reconfigurable devices to efficiently realize the Tor protocol on embedded devices. In particular, this targets the acceleration of the complex cryptographic operations involved in the handshake of routing nodes and the data stream encryption. Our hardware-based implementation on the Xilinx Zynq platform outperforms previous embedded solutions by more than a factor of 9 with respect to the cryptographic handshake - ultimately enabling quite inexpensive but highly efficient routers. Hence, we consider our work as a further milestone towards the development and the dissemination of low-cost and high performance onion relays that hopefully ultimately leads again to a more private Internet.},
	keywords = {cyptographic protocol, encryption, hardware, onion routing protocol, security, THOR},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6913605},
	author = {G{\"u}neys, Tim and Regazzoni, Francesco and Sasdrich, Pascal and Wojcik, Marcin}
}
@conference {82.BeBrFaRe08,
	title = {A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm},
	booktitle = {SECRYPT},
	year = {2008},
	month = {July 26},
	address = {Porto, Portugal},
	abstract = {Due to the diffusion of cryptography in real time applications, performances in cipher and decipher operations are nowadays more important than in the past. On the other side, while facing the problem for embedded systems, additional constraints of area and power consumption must be considered. Many optimized software implementations, instruction set extensions and co-processors, were studied in the past with the aim to either increase performances or to keep the cost low. This paper presents a co-processor that aims to be an intermediate solution, suitable for such applications that require a throughput in the Megabit range and where the die size is a bit relaxed as constraint. To achieve this goal, the core is designed to operate at 32 bits and the throughput is guaranteed by a 2 stage pipeline with data forwarding. The obtained results synthesizing our coprocessor by means of the CMOS $0.18$ $μ$m standard cell library show that the throughput reaches 640 Mbit/s while the circuit size is of only 20 K equivalent gates. },
	keywords = {cryptography, security},
	author = {Bertoni, Guido Marco and Breveglieri, Luca and Farina, Roberto and Regazzoni, Francesco}
}
@conference {29.SaMaRe2005,
	title = {Speeding Security on the Intel StrongARM},
	booktitle = {Embedded Intel Solutions},
	year = {2005},
	pages = {31-33},
	abstract = {With the increasing use of portable and wireless devices in the business and daily life, protecting sensitive information via encryption is becoming more and more crucial. ALaRI (Advanced Learning and Research Institute) has been conducting research aimed at improving the execution of security algorithms in embedded systems. Thanks to a donation from Intel, ALaRI has been able to develop several recommendations for implementing security efficiently on the Intel StrongARM architecture.},
	keywords = {embedded processors, instruction set extension, security},
	author = {Sami, Mariagiovanna and Macchetti, Marco and Regazzoni, Francesco}
}
