@conference {55.DaFeMa, title = {A Memory Unit for Priority Management in IPSec Accelerators}, booktitle = {proceedings of ICC07. Glasgow, Scotland: IEEE Communications Society}, year = {2007}, month = {June 24}, address = {Glasgow, Scotland}, abstract = {This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support Quality of Service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed.}, keywords = {accelerator, IPSec, priority, quality of service (QoS), security, system-on-chip (SoC), SystemC}, doi = {http://dx.doi.org/10.1109/ICC.2007.257}, author = {Dadda, Luigi and Ferrante, Alberto and Macchetti, Marco} }