@conference {17730,
	title = {A Low Overhead Self-adaptation Technique for KPN Applications on NoC-based MPSoCs},
	booktitle = {Proceedings of the 3rd International Conference on Pervasive and Embedded Computing and Communication Systems (PECCS) - Special Session on Self-Adaptive Networked Embedded Systems (SANES)},
	year = {2013},
	month = {February 19-21},
	address = {Barcelona, Spain},
	abstract = {Self-adaptive systems are able to adapt themselves to mutating internal/external conditions so as to meet their goals. One of the challenges to be tackled when designing such systems is the overhead introduced in making the system monitorable and adaptable. A large overhead can easily compensate the benefits of adaptation. In this work, we are addressing this challenge within the context of KPN applications on NoC-based MPSoCs. In particular, parametric adaptations at the application level are considered. We present a low overhead technique for the implementation of the monitor-controller-adapter loop, which is present in self-adaptive systems. The technique is fundamentally based on an extended network interface which provides the ability to interrupt remote tiles on a NoC-based multiprocessor platform. Results from the MJPEG case study show that the proposed interrupt-based approach incurs an overhead as low as 0.4\% without compromising the quality of the adaptation control. Our new technique provides an improvement of approximately 6.25\% compared to another state-of-the-art technique that interacts with the application using KPN semantics (i.e., blocking channels). Moreover, the sensitivity of the overhead to the complexity of the adaptation controller is much lower in case of our interrupt-based technique as compared to the blocking channel based scheme.},
	keywords = {event-based control, kahn process networks (KPN), network-on-chip (NoC), self-adaptivity},
	author = {Derin, Onur and Ramankutty, Prasanth Kuncheerat and Meloni, Paolo and Tuveri, Giuseppe}
}
@article {155.CaDeMeTuSt12.VLSI,
	title = {Adaptivity Support for MPSoCs based on Process Migration in Polyhedral Process Networks},
	journal = {VLSI Design},
	volume = {2012},
	number = {Article ID 987209},
	year = {2012},
	note = {Special issue on Application-Driven Design of Processor, Memory, and Communication Architectures for MPSoCs},
	month = {February},
	pages = {15 pages},
	publisher = {Hindawi},
	abstract = {System adaptivity is becoming an important feature of modern embedded multiprocessor systems. To achieve the goal of system adaptivity when executing Polyhedral Process Networks (PPNs) on a generic tiled Network-on-Chip (NoC) MPSoC platform, we propose an approach to enable the run-time migration of processes among the available platform resources. In our approach, process migration is allowed by a middleware layer which comprises two main components. The first component concerns the inter-tile data communication between processes. We develop and evaluate a number of different communication approaches which implement the semantics of the PPN model of computation on a generic NoC platform. The presented communication approaches do not depend on the mapping of processes, and have been implemented on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented in two case studies with different communication characteristics. The second middleware component allows the actual run-time migration of PPN processes. To this end, we propose and evaluate a process migration mechanism which leverages the PPN model of computation to guarantee a predictable and efficient migration procedure. The efficiency and applicability of the proposed migration mechanism is shown in a real-life case study.},
	keywords = {middleware, network-on-chip (NoC), polyhedral process networks (PPN), process migration, system adaptivity},
	author = {Cannella, Emanuele and Derin, Onur and Meloni, Paolo and Tuveri, Giuseppe and Stefanov, Todor}
}
@conference {17737,
	title = {System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach},
	booktitle = {Proceedings of the 15th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD{\textquoteright}12)},
	year = {2012},
	month = {September 5-8},
	address = {Izmir, Turkey},
	abstract = {Modern embedded systems increasingly require adaptive run-time management. The system may adapt the mapping of the applications in order to accommodate the current workload conditions, to balance load for efficient resource utilization, to meet quality of service agreements, to avoid thermal hot-spots and to reduce power consumption. As the possibility of experiencing run-time faults becomes increasingly relevant with deep-sub-micron technology nodes, in the scope of the MADNESS project, we focus particularly on the problem of graceful degradation by dynamic remapping in presence of run-time faults. In this paper, we summarize the major results achieved in the MADNESS project until now regarding the system adaptivity and fault tolerant processing. We report the first results of the integration between platform level and middleware level support for adaptivity and fault tolerance. A case study demonstrates the survival ability of the platform via a low-overhead process migration mechanism and a near-optimal online remapping heuristic.},
	keywords = {fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), process migration, system adaptivity},
	doi = {http://dx.doi.org/10.1109/DSD.2012.122},
	author = {Meloni, Paolo and Tuveri, Giuseppe and Raffo, Luigi and Cannella, Emanuele and Stefanov, Todor and Derin, Onur and Fiorin, Leandro and Sami, Mariagiovanna}
}
@article {17738,
	title = {Towards Self-adaptive KPN Applications on NoC-based MPSoCs},
	journal = {Advances in Software Engineering},
	volume = {2012},
	year = {2012},
	month = {September},
	pages = {16 pages},
	abstract = {Self-adaptivity is the ability of a system to adapt itself dynamically to internal and external changes. Such a capability helps systems to meet the performance and quality goals, while judiciously using available resources. In this paper, we propose a framework to implement application level self-adaptation capabilities in KPN applications running on NoC-based MPSoCs. The monitor-controller-adapter mechanism is used at the application level. The monitor measures various parameters to check whether the system meets the assigned goals. The controller takes decisions to steer the system towards the goal, which are applied by the adapters. The proposed framework requires minimal modifications to the application code and offers ease of integration. It incorporates a generic adaptation controller based on fuzzy logic. We present the MJPEG encoder as a case study to demonstrate the effectiveness of the approach. Our results show that even if the parameters of the fuzzy controller are not tuned optimally, the adaptation convergence is achieved within reasonable time and error limits. Moreover, the incurred steady-state overhead due to the framework is 4\% for average frame-rate, 3.5\% for average bit-rate, and 0.5\% for additional control data introduced in the network.},
	keywords = {kahn process networks (KPN), network-on-chip (NoC), quality of service (QoS), self-adaptivity},
	doi = {http://dx.doi.org/10.1155/2012/172674},
	author = {Derin, Onur and Ramankutty, Prasanth Kuncheerat and Meloni, Paolo and Cannella, Emanuele}
}
@conference {151.FiMiSa11,
	title = {Design of Fault Tolerant Network Interfaces for NoCs},
	booktitle = {Proceedings of 14th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD{\textquoteright}11)},
	year = {2011},
	month = {September},
	address = {Oulu, Finland},
	keywords = {fault tolerance, network interface, network-on-chip (NoC), system-on-chip (SoC)},
	doi = {http://dx.doi.org/10.1109/DSD.2011.54},
	author = {Fiorin, Leandro and Micconi, Laura and Sami, Mariagiovanna}
}
@article {146.DeDiFi11.IJRC,
	title = {A Middleware Approach to Achieving Fault-tolerance of Kahn Process Networks on Networks-on-Chips},
	journal = {International Journal of Reconfigurable Computing},
	volume = {2011},
	number = {Article ID 295385},
	year = {2011},
	note = {Selected Papers from the International Workshop on Reconfigurable Communication-centric Systems on Chips (ReCoSoC{\textquoteright} 2010)},
	month = {February},
	pages = {14 pages},
	publisher = {Hindawi},
	abstract = {Kahn process networks (KPN) is a distributed model of computation used for describing systems where streams of data are transformed by processes executing in sequence or parallel. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. In this work, we propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network-on-Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault-tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-adaptive Component Run-time Environment) framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.},
	keywords = {fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity},
	issn = {1687-7195},
	doi = {doi:10.1155/2011/295385},
	author = {Derin, Onur and Diken, Erkan and Fiorin, Leandro}
}
@conference {153.CaDeSt11.DASIP,
	title = {Middleware Approaches for Adaptivity of Kahn Process Networks on Networks-on-Chip},
	booktitle = {DASIP{\textquoteright}11: Proceedings of the Conference on Design and Architectures for Signal and Image Processing},
	year = {2011},
	month = {November 2-4},
	pages = {1{\textendash}8},
	address = {Tampere, Finland},
	abstract = {We investigate and propose a number of different middleware approaches, namely virtual connector, virtual connector with variable rate, and request-based, which implement the semantics of Kahn Process Networks on Network-on-Chip architectures. All of the presented solutions allow for run-time system adaptivity. We implement the approaches on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented on two case studies with different communication characteristics. We found out that the virtual connector mechanism outperforms other approaches in the communication-intensive application. In the other case study, which has a higher computation/communication ratio, the middleware approaches show similar performance.},
	keywords = {kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity},
	doi = {http://dx.doi.org/10.1109/DASIP.2011.6136862},
	author = {Cannella, Emanuele and Derin, Onur and Stefanov, Todor}
}
@conference {148.DeKaFi11.NOCS,
	title = {Online Task Remapping Strategies for Fault-tolerant Network-on-Chip Multiprocessors},
	booktitle = {NOCS {\textquoteright}11: Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip},
	year = {2011},
	month = {05/2011},
	pages = {1{\textendash}8},
	address = {Pittsburgh, Pennsylvania, USA},
	abstract = {As CMOS technology scales down into the deep submicron domain, the aspects of fault tolerance in complex Networks-on-Chip (NoCs) architectures are assuming an increasing relevance. Task remapping is a software based solution for dealing with permanent failures in processing elements in the NoC. In this work, we formulate the optimal task mapping problem for mesh-based NoC multiprocessors with deterministic routing as an integer linear programming (ILP) problem with the objective of minimizing the communication traffic in the system and the total execution time of the application. We find the optimal mappings at design time for all scenarios where single-faults occur in the processing nodes. We propose heuristics for the online task remapping problem and compare their performances with the optimal solutions.},
	keywords = {adaptivity, fault tolerance, kahn process networks (KPN), mapping, network-on-chip (NoC), self-adaptivity},
	doi = {http://dx.doi.org/10.1145/1999946.1999967},
	author = {Derin, Onur and Kabakci, Deniz and Fiorin, Leandro}
}
@conference {132.LuNi10,
	title = {Hierarchical Multi-Agent Protection System for NoC based MPSoCs},
	booktitle = {Proceedings of the International Workshop on Security and Dependability for Resource Constrained Embedded Systems (SD4RCES 2010)},
	year = {2010},
	month = {September 14},
	address = {Vienna, Austria},
	abstract = {Network-on-Chip (NoC) has emerged as a promising solution for scalable communication among steadily growing number of cores integrated in MultiProcessor System-on-Chips (MPSoCs). The increasing system heterogeneity together with the possibility of reconfiguration makes the overall system security one of the major concerns in MPSoC design. On the other hand, modular and scalable design of NoCs enables their enhancements in various directions for supporting services other than simple data routing. In this work we propose a conceptual solution to secure NoC based MPSoCs at different levels of design. The basic idea is to integrate various kinds of security approaches from attack specific protection strategies up to system level security. The concept aims at securing single cores but also, at the same time, prevents potential propagation of the attack through the NoC towards. We prove feasibility via prototype realization in FPGA technology.},
	keywords = {multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1145/1868433.1868441},
	author = {Lukovi{\'c}, Slobodan and Christianos, Nikolaos}
}
@conference {136.FiPaSi10,
	title = {A Monitoring System for NoCs},
	booktitle = {Proceedings of the Third International Workshop on Network on Chip Architectures (NoCArc{\textquoteright}2010)},
	year = {2010},
	month = {December},
	address = {Atlanta, Georgia, USA},
	abstract = {In this paper, we propose and discuss a monitoring architecture for Networks-on-Chip (NoCs) that provides system information useful for helping designers in efficiently exploiting resources available in new complex Multiprocessor System-on-Chip (MPSoC) platforms, and in understanding their behavior. We focus on the analysis of the architectural details and design challenges of such systems, by describing power- ful tools for detecting information that can be used both at run-time for detecting dynamic changes in system behavior and at post-execution time for debugging and profiling of applications. We detail the design of the probes monitoring the events and discuss an architecture for collection, storage, and analysis of information generated by them. We evaluate cost of the implementation of the system in terms of area and traffic overhead, and we present results obtained when monitoring a use-case multimedia application.},
	keywords = {hardware counters, network-on-chip (NoC), performance monitoring, system-on-chip (SoC)},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina}
}
@conference {125.DeDi10,
	title = {A Task-aware Middleware for Fault-tolerance and Adaptivity of Kahn Process Networks on Network-on-Chip},
	booktitle = {ReCoSoC 2010: Proceedings of the Fifth International Workshop on Reconfigurable Communication Centric System-on-Chips},
	year = {2010},
	month = {May},
	address = {Karlsruhe, Germany},
	abstract = {We propose a task-aware middleware concept and provide details for its implementation on Network-on-Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault-tolerance strategies for Kahn Process Networks (KPN) applications running on NoCs. In doing that, we extend our SACRE (Self-adaptive Component Run-time Environment) framework by integrating it with an open source NoC simulator, Noxim. We also hope that this work may help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.},
	keywords = {fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity},
	author = {Derin, Onur and Diken, Erkan}
}
@conference {95.FiPaSi09,
	title = {MPSoCs Run-Time Monitoring through Networks-on-Chip},
	booktitle = {The 2009 Conference on Design, Automation and Test In Europe (DATE{\textquoteright}09)},
	year = {2009},
	month = {April/2009},
	address = {Nice, France},
	abstract = {Networks-on-Chip (NoCs) have appeared as design strategy to overcome the limitations, in terms of scalability, efficiency, and power consumption of current buses. In this paper, we discuss the idea of using NoCs to monitor system behaviour at run-time by tracing activities at initiators and targets. Main goal of the monitoring system is to retrieve information useful for run-time optimization and resources allocation in adaptive systems. Information detected by probes embedded within NIs is sent to a central unit, in charge of collecting and elaborating the data. We detail the design of the basic blocks and analyse the overhead associated with the ASIC implementation of the monitoring system, as well as discussing implications in terms of the additional traffic generated in the NoC.},
	keywords = {monitoring, network-on-chip (NoC)},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina}
}
@inbook {92.FiPaSi09.2,
	title = {Security in NoC},
	booktitle = {Networks-on-Chips: Theory and Practice},
	year = {2009},
	pages = {157-194},
	publisher = {Taylor and Francis Group, LLC - CRC Press},
	organization = {Taylor and Francis Group, LLC - CRC Press},
	abstract = {Future integrated systems will contain billion of transistors, composing tens to hundreds of IP cores. These IP cores, implementing emerging complex multimedia and network ap- plications, should be able to deliver rich multimedia and networking services. An efficient cooperation among these IP cores (e.g., efficient data transfers) can be achieved through utilization of the available resources. The design of such complex systems includes several challenges to be addressed. Among others one challenge is to design an on-chip interconnection network that should be able to efficiently connect the IP cores. Another challenge is to derive such an application mapping that will make efficient usage of the available hardware resources . An architecture that is able to accommodate such a high number of cores, satisfying the need for commu- nication and data transfers, is the Network-on-Chip (NoC) architecture. For these reasons Networks-on-Chip become a popular choice for designing the on-chip interconnect for Systems-on-Chip (MPSoCs), and are supported from the industry (such as the Ethereal NoC from Philips, the STNoC from STMicroelectronics and an 80-core NoC from Intel). As it is presented in , the key design challenges of emerging NoC design are a) the communication infrastructure, b) the communication paradigm selection and c) the application mapping optimization.},
	keywords = {network-on-chip (NoC), security},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina and Elmiligi, Haytham},
	editor = {Gebali, Fayez and El-Kharashi, Watheq}
}
@conference {80.LuFi08,
	title = {An Automated Design Flow for NoC-based MPSoCs on FPGA},
	booktitle = {RSP 2008, The 19th IEEE/IFIP International Symposium on Rapid System Prototyping},
	year = {2008},
	month = {June 2-5},
	address = {Monterey, USA/CA},
	abstract = {Increased dynamics of the embedded devices market makes reduced time-to-market emerge as one of most challenging tasks in modern embedded system design. The complexity of Multiprocessor Systems-on-Chip (MPSoCs) rapidly increases and Networks-on-Chips (NoCs) have emerged as design strategy to cope with it. In order to allow fast generation of these platforms in the development phase, a full design flow is required. On the other hand, modern FPGAs provide the possibility for fast and low-cost prototyping, representing an efficient response to these needs. In this paper we present a framework, based on the Xilinx Embedded Development Kit (EDK) design flow, for the generation of MPSoCs based on NoCs. The tool provides system designers with the possibility to easily and quickly generate desired architectures that can be helpful for testing, debugging and verifying purposes. Our integrated design flow takes as input a textual description of the system and produces as final result a configuration bitstream file. The framework has been tested and verified on a Xilinx Virtex-II Pro board.},
	keywords = {FPGA, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), reconfigurable systems, security},
	doi = {http://dx.doi.org/10.1109/RSP.2008.31},
	author = {Lukovi{\'c}, Slobodan and Fiorin, Leandro}
}
@conference {76.FiLuPa08,
	title = {Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoCs},
	booktitle = {Proceedings of the 21st IPDPS 2007 Reconfigurable Architecture Workshop (RAW), 21th IEEE International Parallel and Distributed Processing Symposium},
	year = {2008},
	month = {April},
	address = {Miami, USA/FL},
	abstract = {Security issues are emerging to be a basic concern in modern SoC development. Since in the field of on-chip interconnections the security problem continues to remain mostly an unexplored topic, this paper proposes a novel technique for data protection that uses the communication subsystem as basis. The proposed architecture works as a firewall managing the memory accesses on the basis of a lookup table containing the access rights. This module, called Data Protection Unit (DPU), has been designed for MPSoC architectures and integrated in the Network Interfaces near the shared memory. We implement the DPU inside an MPSoC architecture on FPGA and we add features to the module to be aware of dynamic reconfiguration of the system software. Starting from a general overview of our design down to components structure, we introduce the place and the role of the DPU module inside the system for a reconfigurable secure implementation of a MPSoC on FPGA. The description of the DPU concept, its implementation, and integration into the system are described in detail. Finally, the architecture is fully implemented on FPGA and tested on a Xilinx Virtex-II Pro board.},
	keywords = {data protection, FPGA, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), reconfigurable systems, security},
	doi = {http://dx.doi.org/10.1109/IPDPS.2008.4536514},
	author = {Fiorin, Leandro and Lukovi{\'c}, Slobodan and Palermo, Gianluca}
}
@article {84.AlGaSte2008,
	title = {Secure Memory Accesses on Networks-on-Chip},
	journal = {IEEE Transactions on Computers},
	volume = {57},
	number = {9},
	year = {2008},
	month = {September},
	pages = {1216-1229},
	abstract = {Security is gaining relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses security aspects related to Network on Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based multiprocessor systems, we focus on the topic, not yet thoroughly faced, of data protection. In this paper, we present a secure NoC architecture composed of a set of Data Protection Units (DPUs) implemented within the Network Interfaces (NIs)1. The run-time configuration of the programmable part of the DPUs is managed by a central unit, the Network Security Manager (NSM). The DPU, similar to a firewall, can check and limit the access rights (none, read, write, or both) of processors accessing data and instructions in a shared memory. In particular, the DPU can distinguish between the operating roles (supervisor/user and secure/non secure) of the processing elements.We explore alternative implementations of the DPU and demonstrate how this unit does not affect the network latency if the memory request has the appropriate rights. We also focus on the dynamic updating of the DPUs to support their utilization in dynamic environments, and on the utilization of authentication techniques to increase the level of security.},
	keywords = {data protection, embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1109/TC.2008.69},
	author = {Fiorin, Leandro and Palermo, Gianluca and Lukovi{\'c}, Slobodan and Catalano, Valerio and Silvano, Cristina}
}
@conference {88.FiPaSi08,
	title = {A Security Monitoring Service for NoCs},
	booktitle = {Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS{\textquoteright}08)},
	year = {2008},
	month = {10/2008},
	address = {Atlanta, Georgia, USA.},
	abstract = {As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. Networks-on- Chip (NoCs) have appeared as design strategy to cope with the rapid increase in complexity of Multiprocessor Systems- on-Chip (MPSoCs), but only recently research community have addressed security on NoC-based architectures. In this paper, we present a monitoring system for NoC based architectures, whose goal is to help detect security violations carried out against the system.Information col- lected are sent to a central unit for efficiently counteracting actions performed by attackers.We detail the design of the basic blocks and analyse overhead associated with the ASIC implementation of the monitoring system, discussing type of security threats that it can help detect and counteract.},
	keywords = {embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1145/1450135.1450180},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina}
}
@conference {61.PaMaSiLo07,
	title = {Application-Specific Topology Design Customization for STNoC},
	booktitle = {DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07)},
	year = {2007},
	month = {August 29-31},
	address = {L{\"u}beck, Germany},
	abstract = {Customized network-oriented communication architectures have recently become a must to support high bandwidth SoCs. To this end, a corresponding communication design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a Pareto Simulated Annealing (PSA) approach for the customization of the network topology. The proposed PSA approach has been applied to STNoC, the Network on Chip developed by STMicroelectronics. Starting from the ring topology, the proposed application-specific design flow tries to find a set of customized topologies (optimized in terms of performance and area/energy overhead) by adding custom links up to the spidergon topology.},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/DSD.2007.4341522},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {68.FiPaLuSi07,
	title = {A Data protection Unit for NoC-based Architecture},
	booktitle = {CODES+ISSS 2007, in proceedings of the Fifth IEEE/ACM/FIP International Conference of Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007)},
	year = {2007},
	month = {September 30},
	address = {Salzburg, Austria},
	abstract = {Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next generation embedded devices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network Interface (NI). The DPU supports the capability to check and limit the access rights(none, read, write or both) of processors requesting access to data locations in a shared memory - in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore different alternative implementations and demonstrate how the DPU unit does not affect the network latency if the memory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC implementations of the Data Protection Unit.},
	keywords = {data protection, embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1145/1289816.1289858},
	author = {Fiorin, Leandro and Palermo, Gianluca and Lukovi{\'c}, Slobodan and Silvano, Cristina}
}
@conference {57.PaMaSiLoCo07,
	title = {Mapping and Topology Customization Approaches for Application-Specific STNoC Designs},
	booktitle = {IEEE Proceedings of ASAP{\textquoteright}07 - 18th International Conference on Application-specific Systems, Architectures and Processors},
	year = {2007},
	month = {July},
	address = {Montr{\'e}al, Qu{\'e}bec, Canada},
	abstract = {Application-specific network-oriented communication architectures have recently become an effective solution to support high bandwidth Systems on-Chip. The Network on-Chip architectures considered so far range from regular to fully customized topologies for application specific designs requiring high-level bandwidth. To this end, a networkcentric design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. This paper introduces four different approaches based on the orthogonalization of core mapping and topology customization applied to STNoC, the Network on-Chip developed by STMicroelecronics. The four methods are derived from the combination of the initial mappings to two standard topologies (ring and spidergon) with two types of topology customization based on the insertion of cross-links to reduce the network distance of standard topologies},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/ASAP.2007.4429959},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {73.OtReLa07,
	title = {Rapid Creation of Application Models from Bandwidth Aware Core Graphs},
	booktitle = {Proceedings of: IP Based SoC Design 2007},
	year = {2007},
	month = {December 5-6},
	address = {Grenoble, France},
	abstract = {We present a methodology that allows rapid creation of application models from bandwidth aware core graphs that are available in the literature for a wide range of applications and we discuss their applicability to the rapid exploration of multiple Networks on Chip (NoCs) layout organizations. In a bandwidth aware core graph, each node represents a core and the numbers on the edges represent the bandwidth requirements between cores. We describe core graphs in a UML object model diagram and we then have an automatic code generation tool which produces a SystemC description whose behaviour results in a packet generation on every output connection that respects the bandwidth requirements specified in the core graph. We can then rapidly derive a NoC mapping in which a specific floorplan of the cores can be evaluated and compared with alternate floorplan options for rapid design space exploration.},
	keywords = {network-on-chip (NoC), rapid prototyping},
	author = {Otero, Jo{\~a}o and Regazzoni, Francesco and Lajolo, Marcello}
}
@conference {60.FiSiSa07,
	title = {Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations},
	booktitle = {DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07)},
	year = {2007},
	month = {August 29-31},
	address = {L{\"u}beck, Germany},
	abstract = {Security has gained increasing relevance in the development of embedded devices. Towards the aim of a secure system at each level of the design, in this paper we address security aspects related to Networks-on-Chips (NoCs) architectures. After presenting the attacks most likely to address NoCs, we survey existing academic and industrial secure architectures relevant to our case, focusing in particular on their communication infrastructure. We outline and propose possible solutions to contrast some of the attacks described and suggest the use of the NoC as a mean to monitor and detect unexpected system behaviors.},
	keywords = {embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1109/DSD.2007.4341520},
	author = {Fiorin, Leandro and Silvano, Cristina and Sami, Mariagiovanna}
}
@conference {66.PaMaSi07,
	title = {A Topology Design Customization Approach for (STNoC)},
	booktitle = {Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007).},
	year = {2007},
	month = {September 24-26},
	address = {Catania, Italy},
	abstract = {To support high bandwidth SoCs, a communication design flow is necessary for the design space exploration respecting tight design requirements. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a design flow for the core mapping and customization of the network topology applied to STNoC, the Network on-Chip developed by STMicroelectronics. Starting from ring topology, the proposed application-specific flow tries to find a set of customized topologies, optimized in terms of performance and area/energy overhead, by adding links. The generated STNoC custom topologies provide a reduced cost with respect to the spidergon topology.},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/ASAP.2007.4429959},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {37.RegLaj2005,
	title = {Hardware/Software Partitioning and Interface Synthesis in Networks On Chip},
	booktitle = {IP Based SoC Design 2005},
	year = {2005},
	month = {December 7-8},
	address = {Grenoble, France},
	abstract = {With deep sub-micron technology, chip designers are expected to create System-On-Chip (SOC) solutions by connecting different Intellectual Property (IP) blocks using efficient and reliable interconnection schemes. On chip networks are quite compelling because, by applying networking techniques to on-chip communication, they allow to implement a fully distributed communication pattern with little or no global coordination. This avoids the problems due to the difficulty of implementing future chips with one single clock source and negligible skew. On the other hand, in order to benefit from the NOC communication paradigm, designers should perform a careful functional mapping for taking advantage of spatial locality, by placing the blocks that communicate more frequently closer together. This reduces the use of long global paths and the corresponding energy dissipation. In this work we show how a tile based NOC architecture can be exploited in order to support a flexible hardware/software partitioning of a system-level specification and we present a methodology for the automatic synthesis of the hardware/software interfaces.},
	keywords = {HW/SW co-design, network-on-chip (NoC), system-on-chip (SoC)},
	author = {Regazzoni, Francesco and Lajolo, Marcello}
}
