@conference {54.FePi07,
	title = {High-level Architecture of an IPSec-dedicated System on Chip},
	booktitle = {proceedings of NGI 2007},
	year = {2007},
	month = {May},
	publisher = {IEEE Press},
	organization = {IEEE Press},
	address = {Trondheim, Norway},
	abstract = {IPSec is a suite of protocols which adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. In this paper we propose a high level architecture of a System on Chip (SoC) which implements IPSec. This SoC has been thought to be placed on the main data path of the host machine (flow-through architecture), thus allowing for transparent processing of IPSec traffic. The functionalities of the different blocks and their interactions, along with an estimation of the internal memory size, are also shown.},
	keywords = {accelerator, IPSec, priority, quality of service (QoS), security, system-on-chip (SoC), SystemC},
	author = {Ferrante, Alberto and Piuri, Vincenzo}
}
@conference {55.DaFeMa,
	title = {A Memory Unit for Priority Management in IPSec Accelerators},
	booktitle = {proceedings of ICC07. Glasgow, Scotland: IEEE Communications Society},
	year = {2007},
	month = {June 24},
	address = {Glasgow, Scotland},
	abstract = {This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support Quality of Service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed.},
	keywords = {accelerator, IPSec, priority, quality of service (QoS), security, system-on-chip (SoC), SystemC},
	doi = {http://dx.doi.org/10.1109/ICC.2007.257},
	author = {Dadda, Luigi and Ferrante, Alberto and Macchetti, Marco}
}
@conference {58.FeChPi07,
	title = {A Query Unit for the IPSec Databases},
	booktitle = {SECRYPT 2007},
	year = {2007},
	month = {07/2007},
	address = {Barcelona, Spain},
	abstract = {IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within IPSec make extensive use of two databases, namely the Security Policy Database (SPD) and the Security Association Database (SAD). The ability to query the SPD quickly is fundamental as this operation needs to be done for each incoming or outgoing IP packet, even if no IPSec processing needs to be applied on it. This may easily result in millions of query per second in gigabit networks. Since the databases may be of several thousands of records on large secure gateways, a dedicated hardware solution is needed to support high throughput. In this paper we discuss an architecture for these query units, we propose different query methods for the two databases, and we compare them through simulation. Two different versions of the architecture are presented: the basic version is modified to support multithreading. As shown by the simulations, this technique is very effective in this case. The architecture that supports multithreading allows for 11 million queries per second in the best case.},
	keywords = {accelerator, database, IPSec, security, security association database (SAD), security policy database (SPD), system-on-chip (SoC), SystemC},
	author = {Ferrante, Alberto and Chandra, Satish and Piuri, Vincenzo}
}
@conference {64.Barcellona2,
	title = {SC2: State Charts to System C: Automatic Executable Models Generation},
	booktitle = {proceedings FDL07},
	year = {2007},
	month = {September},
	address = {Barcelona, Spain},
	abstract = {The recent development of embedded systems calls for the necessity of a complete framework for design and simulation of applications that span through all levels of system design. Desirable characteristics of such a framework are rapidity of use, simplicity and reusability. For this purpose we already introduced a generator that converts specifications written with a subset of StateCharts to behavioral SystemC [9] [11]. In this paper we present the new version of our tool: most of the limitations of the previous versions have been overcome, the considered subset of the StateCharts formalism has been extended and the target has been changed from behavioral to Register Tranfer Level (RTL) SystemC. A major enhancement of this new version is the possibility of obtaining various module instances starting from a single specification, which is vital in some contexts (e.g. Wireless Sensors Networks simulation). The semantics chosen for our StateCharts diagrams is clearly described. The generation of executable models as well as the kernel template of the generated code are discussed in detail.},
	keywords = {code generation, StateCharts, SystemC, unified modeling language (UML)},
	author = {Mura, Marcello and Paolieri, Marco}
}
@conference {50.MuPaNeSa07,
	title = {StateCharts to SystemC: a High Level Hardware Simulation Approach},
	booktitle = {Proceedings of GLSVLSI 2007},
	year = {2007},
	month = {March 11-13},
	address = {Stresa, Italy},
	abstract = {In this paper we present a tool that converts specifications written with a subset of StateCharts into SystemC behavioral models. The main advantages of such an approachare rapidity of use, simplicity and reusability. Various systems can be modeled at different levels of abstraction and accuracy through StateCharts and different peculiar aspects (e.g. energy, performances) can be taken into consideration. Moreover different parts of the design can be identified at different detail levels. The kernel of the simulator is fully discussed together with its mapping to the semantics of our StateCharts diagrams. As a case study we present here a model of the IBM PowerPC 750 Cache system and the respective SystemC simulator automatically generated by our tool.},
	keywords = {code generation, StateCharts, SystemC, unified modeling language (UML)},
	doi = {http://dx.doi.org/10.1145/1228784.1228904},
	author = {Mura, Marcello and Paolieri, Marco and Negri, Luca and Sami, Mariagiovanna}
}
