@article {18050, title = {A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.}, journal = {Microprocessors and Microsystems - Embedded Hardware Design}, volume = {37}, issue = {6-7}, year = {2013}, pages = {515{\textendash}529}, doi = {10.1016/j.micpro.2013.07.007}, author = {Derin, Onur and Cannella, Emanuele and Tuveri, Giuseppe and Meloni, Paolo and Stefanov, Todor and Fiorin, Leandro and Raffo, Luigi and Sami, Mariagiovanna} } @article {155.CaDeMeTuSt12.VLSI, title = {Adaptivity Support for MPSoCs based on Process Migration in Polyhedral Process Networks}, journal = {VLSI Design}, volume = {2012}, number = {Article ID 987209}, year = {2012}, note = {Special issue on Application-Driven Design of Processor, Memory, and Communication Architectures for MPSoCs}, month = {February}, pages = {15 pages}, publisher = {Hindawi}, abstract = {System adaptivity is becoming an important feature of modern embedded multiprocessor systems. To achieve the goal of system adaptivity when executing Polyhedral Process Networks (PPNs) on a generic tiled Network-on-Chip (NoC) MPSoC platform, we propose an approach to enable the run-time migration of processes among the available platform resources. In our approach, process migration is allowed by a middleware layer which comprises two main components. The first component concerns the inter-tile data communication between processes. We develop and evaluate a number of different communication approaches which implement the semantics of the PPN model of computation on a generic NoC platform. The presented communication approaches do not depend on the mapping of processes, and have been implemented on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented in two case studies with different communication characteristics. The second middleware component allows the actual run-time migration of PPN processes. To this end, we propose and evaluate a process migration mechanism which leverages the PPN model of computation to guarantee a predictable and efficient migration procedure. The efficiency and applicability of the proposed migration mechanism is shown in a real-life case study.}, keywords = {middleware, network-on-chip (NoC), polyhedral process networks (PPN), process migration, system adaptivity}, author = {Cannella, Emanuele and Derin, Onur and Meloni, Paolo and Tuveri, Giuseppe and Stefanov, Todor} } @conference {17737, title = {System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach}, booktitle = {Proceedings of the 15th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD{\textquoteright}12)}, year = {2012}, month = {September 5-8}, address = {Izmir, Turkey}, abstract = {Modern embedded systems increasingly require adaptive run-time management. The system may adapt the mapping of the applications in order to accommodate the current workload conditions, to balance load for efficient resource utilization, to meet quality of service agreements, to avoid thermal hot-spots and to reduce power consumption. As the possibility of experiencing run-time faults becomes increasingly relevant with deep-sub-micron technology nodes, in the scope of the MADNESS project, we focus particularly on the problem of graceful degradation by dynamic remapping in presence of run-time faults. In this paper, we summarize the major results achieved in the MADNESS project until now regarding the system adaptivity and fault tolerant processing. We report the first results of the integration between platform level and middleware level support for adaptivity and fault tolerance. A case study demonstrates the survival ability of the platform via a low-overhead process migration mechanism and a near-optimal online remapping heuristic.}, keywords = {fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), process migration, system adaptivity}, doi = {http://dx.doi.org/10.1109/DSD.2012.122}, author = {Meloni, Paolo and Tuveri, Giuseppe and Raffo, Luigi and Cannella, Emanuele and Stefanov, Todor and Derin, Onur and Fiorin, Leandro and Sami, Mariagiovanna} } @conference {153.CaDeSt11.DASIP, title = {Middleware Approaches for Adaptivity of Kahn Process Networks on Networks-on-Chip}, booktitle = {DASIP{\textquoteright}11: Proceedings of the Conference on Design and Architectures for Signal and Image Processing}, year = {2011}, month = {November 2-4}, pages = {1{\textendash}8}, address = {Tampere, Finland}, abstract = {We investigate and propose a number of different middleware approaches, namely virtual connector, virtual connector with variable rate, and request-based, which implement the semantics of Kahn Process Networks on Network-on-Chip architectures. All of the presented solutions allow for run-time system adaptivity. We implement the approaches on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented on two case studies with different communication characteristics. We found out that the virtual connector mechanism outperforms other approaches in the communication-intensive application. In the other case study, which has a higher computation/communication ratio, the middleware approaches show similar performance.}, keywords = {kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity}, doi = {http://dx.doi.org/10.1109/DASIP.2011.6136862}, author = {Cannella, Emanuele and Derin, Onur and Stefanov, Todor} }