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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleExecutable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities
Publication TypeConference Paper
Year of Publication2008
AuthorsMura, M., A. Panda, and M. Prevostini
Conference NameProceedings of MARTE Workshop (DATE08)
Date PublishedMarch
Conference LocationMunich, Germany
Keywordsautomatic generation of code, high level design, profiling, unified modeling language (UML)

In this paper two well known UML profiles, namely SysML and MARTE are closely examined and compared. Both profiles are well suited for the description of embedded systems, although focusing on different aspects and can therefore be considered as complementary. While SysML targets system engineering descriptions in a high level of abstraction and provide diagrams for requirements specification, MARTE is tailored for systems in which Real Time constraints play a major role. Expressiveness of such profiles and their matching with languages that represent the next step in the development of Hardware/Software systems will be the main subject of this work. A Wireless Sensor Network scenario is taken as a reference case study and used to illustrate a practical application of MDA.