|Title||Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities|
|Publication Type||Conference Paper|
|Year of Publication||2008|
|Authors||Mura, M., A. Panda, and M. Prevostini|
|Conference Name||Proceedings of MARTE Workshop (DATE08)|
|Conference Location||Munich, Germany|
|Keywords||automatic generation of code, high level design, profiling, unified modeling language (UML)|
In this paper two well known UML profiles, namely SysML and MARTE are closely examined and compared. Both profiles are well suited for the description of embedded systems, although focusing on different aspects and can therefore be considered as complementary. While SysML targets system engineering descriptions in a high level of abstraction and provide diagrams for requirements specification, MARTE is tailored for systems in which Real Time constraints play a major role. Expressiveness of such profiles and their matching with languages that represent the next step in the development of Hardware/Software systems will be the main subject of this work. A Wireless Sensor Network scenario is taken as a reference case study and used to illustrate a practical application of MDA.