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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleEnergy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering
Publication TypeConference Paper
Year of Publication2002
AuthorsBona, A., M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, and R. Zafalon
Conference Name39th Design Automation Conference
Date PublishedJune 10-14
Conference LocationNew Orleans
Keywordspower estimation, VLIW architectures
Abstract

Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction, to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor, a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1:9% between the cluster-based estimation model and the reference design, with a standard deviation of 5:8%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12%.

DOI10.1109/DAC.2002.1012747