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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleDevelopment cost and size estimation starting from high-level specifications
Publication TypeConference Paper
Year of Publication2001
AuthorsFornaciari, W., F. Salice, U. Bondi, and E. Magini
Conference NameCODES '01: Proceedings of the ninth international symposium on Hardware/software codesign
PublisherACM Press, New York, USA
Conference LocationCopenhagen, Denmark
ISBN Number1-58113-364-2
Keywordsconcurrent engineering, design reuse, process management, project size estimation, VHDL
Abstract

This paper addresses the problem of estimating cost and development effort of a system, starting from its complete or partial high-level description. In addition, some modifications to evaluate the cost-effectiveness of reusing VHDL-based designs, are presented. The proposed approach has been formalized using an approach similar to the COCOMO analysis strategy, enhanced by a project size prediction methodology based on a VHDL function point metric. The proposed design size estimation methodology has been validated through a significant benchmark. The LEON-I microprocessor, whose VHDL description is of public domain.

DOI10.1109/HSC.2001.924656