ALaRI Hang Glider

Search form

Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
TitleAn Automated Design Flow for NoC-based MPSoCs on FPGA
Publication TypeConference Paper
Year of Publication2008
AuthorsLuković, S., and L. Fiorin
Conference NameRSP 2008, The 19th IEEE/IFIP International Symposium on Rapid System Prototyping
Date PublishedJune 2-5
Conference LocationMonterey, USA/CA
KeywordsFPGA, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), reconfigurable systems, security
Abstract

Increased dynamics of the embedded devices market makes reduced time-to-market emerge as one of most challenging tasks in modern embedded system design. The complexity of Multiprocessor Systems-on-Chip (MPSoCs) rapidly increases and Networks-on-Chips (NoCs) have emerged as design strategy to cope with it. In order to allow fast generation of these platforms in the development phase, a full design flow is required. On the other hand, modern FPGAs provide the possibility for fast and low-cost prototyping, representing an efficient response to these needs. In this paper we present a framework, based on the Xilinx Embedded Development Kit (EDK) design flow, for the generation of MPSoCs based on NoCs. The tool provides system designers with the possibility to easily and quickly generate desired architectures that can be helpful for testing, debugging and verifying purposes. Our integrated design flow takes as input a textual description of the system and produces as final result a configuration bitstream file. The framework has been tested and verified on a Xilinx Virtex-II Pro board.

DOI10.1109/RSP.2008.31